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Features
* MPEG I/II-Layer 3 Hardwired Decoder
- Stand-alone MP3 Decoder - 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency - Separated Digital Volume Control on Left and Right Channels (Software Control using 31 Steps) - Bass, Medium, and Treble Control (31 Steps) - Bass Boost Sound Effect - Ancillary Data Extraction - CRC Error and MPEG Frame Synchronization Indicators Programmable Audio Output for Interfacing with Common Audio DAC - PCM Format Compatible - I2S Format Compatible 8-bit MCU C51 Core Based (FMAX = 20 MHz) 2304 Bytes of Internal RAM 64K Bytes of Code Memory - AT89C51SND1C: Flash (100K Erase/Write Cycles) - AT83C51SND1C: ROM 4K Bytes of Boot Flash Memory (AT89C51SND1C) - ISP: Download from USB or UART USB Rev 1.1 Controller - Full Speed Data Transmission Built-in PLL - MP3 Audio Clocks - USB Clock MultiMedia Card(R) Interface Compatibility Atmel DataFlash(R) SPI Interface Compatibility IDE/ATAPI Interface 2 Channels 10-bit ADC, 8 kHz (8-true bit) - Battery Voltage Monitoring - Voice Recording Controlled by Software Up to 44 Bits of General-purpose I/Os - 4-bit Interrupt Keyboard Port for a 4 x n Matrix - SmartMedia(R) Software Interface 2 Standard 16-bit Timers/Counters Hardware Watchdog Timer Standard Full Duplex UART with Baud Rate Generator Two Wire Master and Slave Modes Controller SPI Master and Slave Modes Controller Power Management - Power-on Reset - Software Programmable MCU Clock - Idle Mode, Power-down Mode Operating Conditions: - 3V, 10%, 25 mA Typical Operating at 25C - Temperature Range: -40C to +85C Packages - TQFP80, BGA81, PLCC84 (Development Board) - Dice
* * * * * * * * * * * * * * * * * *
Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
AT83C51SND1C AT89C51SND1C Preliminary
* *
Description
The AT8xC51SND1C are fully integrated stand-alone hardwired MPEG I/II-Layer 3 decoder with a C51 microcontroller core handling data flow and MP3-player control. The AT89C51SND1C includes 64K Bytes of Flash memory and allows In-System Programming through an embedded 4K Bytes of Boot Flash memory.
Rev. 4109E-8051-06/03
The AT83C51SND1C includes 64K Bytes of ROM memory. The AT8xC51SND1C include 2304 Bytes of RAM memory. The AT8xC51SND1C provides the necessary features for human interface like timers, keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), ADC input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards).
Typical Applications
* * * *
MP3-Player PDA, Camera, Mobile Phone MP3 Car Audio/Multimedia MP3 Home Audio/Multimedia MP3
Block Diagram
Figure 1. AT8xC51SND1C Block Diagram
INT0 INT1 VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0 TXD RXD T0 T1 SS MISO MOSI SCK SCL SDA
3
3 Interrupt Handler Unit Flash ROM 64 KBytes Flash Boot 4 KBytes
3
3
3
3
4
4
4
4
1
1
RAM 2304 Bytes
10-bit A to D Converter or 10-bit ADC
UART and BRG
Timers 0/1 Watchdog
SPI/DataFlash Controller
TWI Controller
C51 (X2 Core)
8-Bit Internal Bus
Clock and PLL Unit
MP3 Decoder Unit
I2S/PCM Audio Interface
USB Controller
MMC Interface
Keyboard Interface
I/O Ports IDE Interface
1
FILT X1 X2 RST ISP ALE DOUT DCLK DSEL SCLK D+ DMCLK MDAT MCMD KIN3:0 P0-P5
1 Alternate function of Port 1 3 Alternate function of Port 3 4 Alternate function of Port 4
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Pin Description
Pinouts
Figure 2. AT89C51SND1C 80-pin QFP Package
P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
ALE ISP/NC(1) P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA VDD PVDD FILT PVSS VSS X2 X1 TST UVDD UVSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
AT89C51SND1C-RO (FLASH) AT83C51SND1C-RO (ROM)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD
Note:
1. ISP pin is only available in AT89C51SND1C product. Do not connect this pin on AT83C51SND1C product.
D+ DVDD VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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Figure 3. AT8xC51SND1C 81-pin BGA Package
9
P4.6
8
P2.0/ A8
7
P4.0/ MISO P4.1/ MOSI P2.1/ A9
6
P4.2/ SCK P4.3/ SS
5
VDD
4
P0.2/ AD2 P0.4/ AD4
3
P0.3/ AD3 P0.0/ AD0 P1.0/ KIN0 P1.7/ SDA
2
P5.0
1
ALE
A B C D E F G H J
P4.4
P4.7
P0.1/ AD1
ISP/ NC(1) P1.3/ KIN3
P1.1
P2.5/ A13 P2.4/ A12
P2.2/ A10 P2.6/ A14 P2.3/ A11
P0.6
VSS
P5.1
P1.2/ KIN2
P4.5
P0.7/ AD7 P2.7/ A15
P0.5/ AD5
P1.6/ SCL
P1.5
P1.4
VDD
VSS
FILT
PVDD
X1
VDD
RST
MCMD
MCLK
MDAT
AVDD
P3.4/ T0 P3.5/ T1 P3.3/ INT1 P3.2/ INT0
UVSS
PVSS
X2
DSEL
SCLK
DOUT
P5.3
P3.7/ RD
VDD
TST
VSS
DCLK
VSS
AIN1
AVSS
AIN0
P3.1/ TXD P3.0/ RXD
D-
UVDD
VDD
P5.2
AREFP
AREFN
P3.6/ WR
VSS
D+
Note:
1. ISP pin is only available in AT89C51SND1C product. Do not connect this pin on AT83C51SND1C product.
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Figure 4. AT8xC51SND1C 84-pin PLCC Package
NC P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 ALE ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA VDD PAVDD FILT PAVSS VSS X2 NC X1 TST UVDD UVSS 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
AT89C51SND1C-SR (FLASH)
NC P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD
D+ DVDD VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 NC
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
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Signals
All the AT8xC51SND1C signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description
Signal Name Type Description Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS. Port 1 P1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups. Alternate Function
P0.7:0
I/O
AD7:0
P1.7:0
I/O
KIN3:0 SCL SDA A15:8 RXD TXD
P2.7:0
I/O
P3.7:0
I/O
Port 3 P3 is an 8-bit bidirectional I/O port with internal pull-ups.
INT0 INT1 T0 T1 WR RD MISO MOSI SCK SS -
P4.7:0
I/O
Port 4 P4 is an 8-bit bidirectional I/O port with internal pull-ups.
P5.3:0
I/O
Port 5 P5 is a 4-bit bidirectional I/O port with internal pull-ups.
Table 2. Clock Signal Description
Signal Name Type Description Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. X1 is the clock source for internal timing. Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave X2 unconnected. PLL Low Pass Filter input FILT receives the RC network of the PLL low pass filter. Alternate Function
X1
I
-
X2
O
-
FILT
I
-
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Table 3. Timer 0 and Timer 1 Signal Description
Signal Name Type Description Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. INT0 I External Interrupt 0 INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is set by a low level on INT0#. Timer 1 Gate Input INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. INT1 I External Interrupt 1 INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1#. If bit IT1 is cleared, bit IE1 is set by a low level on INT1#. Timer 0 External Clock Input When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. Timer 1 External Clock Input When timer 1 operates as a counter, a falling edge on the T1 pin increments the count. P3.3 P3.2 Alternate Function
T0
I
P3.4
T1
I
P3.5
Table 4. Audio Interface Signal Description
Signal Name DCLK DOUT DSEL Type O O O Description DAC Data Bit Clock DAC Audio Data DAC Channel Select Signal DSEL is the sample rate clock output. DAC System Clock SCLK is the oversampling clock synchronized to the digital audio data (DOUT) and the channel selection signal (DSEL). Alternate Function -
SCLK
O
-
Table 5. USB Controller Signal Description
Signal Name Type Description USB Positive Data Upstream Port This pin requires an external 1.5 K pull-up to VDD for full speed operation. USB Negative Data Upstream Port Alternate Function
D+
I/O
-
D-
I/O
-
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Table 6. MutiMediaCard Interface Signal Description
Signal Name MCLK Type O Description MMC Clock output Data or command clock transfer. MMC Command line Bidirectional command channel used for card initialization and data transfer commands. To avoid any parasitic current consumption, unused MCMD input must be polarized to VDD or VSS. MMC Data line Bidirectional data channel. To avoid any parasitic current consumption, unused MDAT input must be polarized to VDD or VSS. Alternate Function -
MCMD
I/O
-
MDAT
I/O
-
Table 7. UART Signal Description
Signal Name Type Description Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. Alternate Function
RXD
I/O
P3.0
TXD
O
P3.1
Table 8. SPI Controller Signal Description
Signal Name Type Description SPI Master Input Slave Output Data Line When in master mode, MISO receives data from the slave peripheral. When in slave mode, MISO outputs data to the master controller. SPI Master Output Slave Input Data Line When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller. SPI Clock Line When in master mode, SCK outputs clock to the slave peripheral. When in slave mode, SCK receives clock from the master controller. SPI Slave Select Line When in controlled slave mode, SS enables the slave mode. Alternate Function
MISO
I/O
P4.0
MOSI
I/O
P4.1
SCK
I/O
P4.2
SS
I
P4.3
Table 9. TWI Controller Signal Description
Signal Name Type Description TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to the slave peripherals. When TWI controller is in slave mode, SCL receives clock from the master controller. TWI Serial Data SDA is the bidirectional Two Wire data line. Alternate Function
SCL
I/O
P1.6
SDA
I/O
P1.7
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Table 10. A/D Converter Signal Description
Signal Name AIN1:0 AREFP AREFN Type I I I Description A/D Converter Analog Inputs Analog Positive Voltage Reference Input Analog Negative Voltage Reference Input This pin is internally connected to AVSS. Alternate Function -
Table 11. Keypad Interface Signal Description
Signal Name Type Description Keypad Input Lines Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. Alternate Function
KIN3:0
I
P1.3:0
Table 12. External Access Signal Description
Signal Name Type Description Address Lines Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. Address/Data Lines Multiplexed lower address and data lines for the external memory or the IDE interface. Address Latch Enable Output ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A7:0. An external latch is used to demultiplex the address from address/data bus. ISP Enable Input AT89C51SND1C Only This signal must be held to GND through a pull-down resistor at the falling reset to force execution of the internal bootloader. Read Signal Read signal asserted during external data memory read operation. Write Signal Write signal asserted during external data memory write operation. Alternate Function
A15:8
I/O
P2.7:0
AD7:0
I/O
P0.7:0
ALE
O
-
ISP
I/O
-
RD
O
P3.7
WR
O
P3.6
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Table 13. System Signal Description
Signal Name Type Description Reset Input Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal operation. Test Input Test mode entry signal. This pin must be set to VDD. Alternate Function
RST
I
-
TST
I
-
Table 14. Power Signal Description
Signal Name VDD Type PWR Description Digital Supply Voltage Connect these pins to +3V supply voltage. Circuit Ground Connect these pins to ground. Analog Supply Voltage Connect this pin to +3V supply voltage. Analog Ground Connect this pin to ground. PLL Supply voltage Connect this pin to +3V supply voltage. PLL Circuit Ground Connect this pin to ground. USB Supply Voltage Connect this pin to +3V supply voltage. USB Ground Connect this pin to ground. Alternate Function -
VSS
GND
-
AVDD
PWR
-
AVSS
GND
-
PVDD
PWR
-
PVSS
GND
-
UVDD
PWR
-
UVSS
GND
-
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Internal Pin Structure
Table 15. Detailed Internal Pin Structure
Circuit(1)
VDD
Type
Pins
RTST
Input
TST
VDD
Watchdog Output
P Input/Output
RRST
RST
VSS
2 osc periods Latch Output
VDD
VDD
VDD
P1
P2
P3 Input/Output
N
VSS VDD
P1(2) P2(3) P3 P4 P53:0
P Input/Output N
VSS VDD
P0 MCMD MDAT ISP
P Output N
VSS
ALE SCLK DCLK DOUT DSEL MCLK
D+ D-
Input/Output
D+ D-
Notes:
1. For information on resistors value, input/output levels, and drive capability, refer to the Section "DC Characteristics", page 181. 2. When the Two Wire controller is enabled, P1, P2, and P3 transistors are disabled allowing pseudo open-drain structure. 3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8).
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Clock Controller
The AT8xC51SND1C clock controller is based on an on-chip oscillator feeding an onchip Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this controller. The AT8xC51SND1C X1 and X2 pins are the input and the output of a single-stage onchip inverter (see Figure 5) that can be configured with off-chip components such as a Pierce oscillator (see Figure 6). Value of capacitors and crystal characteristics are detailed in the section "DC Characteristics". The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU core, and a clock for the peripherals as shown in Figure 5. These clocks are either enabled or disabled, depending on the power reduction mode as detailed in the section "Power Management" on page 46. The peripheral clock is used to generate the Timer 0, Timer 1, MMC, ADC, SPI, and Port sampling clocks. Figure 5. Oscillator Block Diagram and Symbol
/2
Oscillator
X1
0 1
Peripheral Clock CPU Core Clock
X2 X2
CKCON.0
IDL
PCON.0
PD
PCON.1
Oscillator Clock
CPU CLOCK OSC CLOCK
PER CLOCK
Peripheral Clock Symbol
CPU Core Clock Symbol
Oscillator Clock Symbol
Figure 6. Crystal Connection
X1
C1 Q C2
VSS
X2
X2 Feature
Unlike standard C51 products that require 12 oscillator clock periods per machine cycle, the AT8xC51SND1C need only 6 oscillator clock periods per machine cycle. This feature called the "X2 feature" can be enabled using the X2 bit(1) in CKCON (see Table 16) and allows the AT8xC51SND1C to operate in 6 or 12 oscillator clock periods per machine cycle. As shown in Figure 5, both CPU and peripheral clocks are affected by this feature. Figure 7 shows the X2 mode switching waveforms. After reset the standard mode is activated. In standard mode the CPU and peripheral clock frequency is the oscillator frequency divided by 2 while in X2 mode, it is the oscillator frequency.
Note: 1. The X2 bit reset value depends on the X2B bit in the Hardware Security Byte (see Table 22 on page 22). Using the AT89C51SND1C (Flash Version) the system can boot either in standard or X2 mode depending on the X2B value. Using AT83C51SND1C (ROM Version) the system always boots in standard mode. X2B bit can be changed to X2 mode later by software.
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Figure 7. Mode Switching Waveforms
X1 X1 / 2 X2 Bit Clock STD Mode X2 Mode(1) STD Mode
Note:
1. In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (timers, etc.) will have their time reference divided by 2. For example, a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms.
PLL
PLL Description The AT8xC51SND1C PLL is used to generate internal high frequency clock (the PLL Clock) synchronized with an external low-frequency (the Oscillator Clock). The PLL clock provides the MP3 decoder, the audio interface, and the USB interface clocks. Figure 8 shows the internal structure of the PLL. The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the comparison between the reference clock coming from the N divider and the reverse clock coming from the R divider and generates some pulses on the Up or Down signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the clock generation. When the PLL is locked, the bit PLOCK in PLLCON register (see Table 17) is set. The CHP block is the Charge Pump that generates the voltage reference for the VCO by injecting or extracting charges from the external filter connected on PFILT pin (see Fi gure 9) . Value of the filter components ar e detailed in the Section " DC Characteristics". The VCO block is the Voltage Controlled Oscillator controlled by the voltage Vref produced by the charge pump. It generates a square wave signal: the PLL clock. Figure 8. PLL Block Diagram and Symbol
PLLCON.1
PFILT
PLLEN N divider
OSC CLOCK
N6:0
Up PFLD Down PLOCK
PLLCON.0
CHP
Vref
VCO
PLL Clock
R divider R9:0
OSCclk x ( R + 1 ) PLLclk = ---------------------------------------------N+1
PLL CLOCK
PLL Clock Symbol
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Figure 9. PLL Filter Connection
FILT
R C1
VSS VSS
C2
PLL Programming
The PLL is programmed using the flow shown in Figure 10. As soon as clock generation is enabled, the user must wait until the lock indicator is set to ensure the clock output is stable. The PLL clock frequency will depend on MP3 decoder clock and audio interface clock frequencies. Figure 10. PLL Programming Flow
PLL Programming
Configure Dividers N6:0 = xxxxxxb R9:0 = xxxxxxxxxxb
Enable PLL PLLRES = 0 PLLEN = 1
PLL Locked?
PLOCK = 1?
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Registers
Table 16. CKCON Register CKCON (S:8Fh) - Clock Control Register
7 Bit Number 7 6 WDX2 5 4 3 2 T1X2 1 T0X2 0 X2
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Watchdog Clock Control Bit Set to select the oscillator clock divided by 2 as watchdog clock input (X2 independent). Clear to select the peripheral clock as watchdog clock input (X2 dependent). Reserved The values read from these bits are indeterminate. Do not set these bits. Timer 1 Clock Control Bit Set to select the oscillator clock divided by 2 as timer 1 clock input (X2 independent). Clear to select the peripheral clock as timer 1 clock input (X2 dependent). Timer 0 Clock Control Bit Set to select the oscillator clock divided by 2 as timer 0 clock input (X2 independent). Clear to select the peripheral clock as timer 0 clock input (X2 dependent). System Clock Control Bit Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER = FOSC/2). Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC).
6
WDX2
5-3
-
2
T1X2
1
T0X2
0
X2
Reset Value = 0000 000Xb (AT89C51SND1C) or 0000 0000b (AT83C51SND1C) Table 17. PLLCON Register PLLCON (S:E9h) - PLL Control Register
7 R1 Bit Number 7-6 5-4 6 R0 5 4 3 PLLRES 2 1 PLLEN 0 PLOCK
Bit Mnemonic Description R1:0 PLL Least Significant Bits R Divider 2 LSB of the 10-bit R divider. Reserved The values read from these bits are always 0. Do not set these bits. PLL Reset Bit Set this bit to reset the PLL. Clear this bit to free the PLL and allow enabling. Reserved The value read from this bit is always 0. Do not set this bit. PLL Enable Bit Set to enable the PLL. Clear to disable the PLL. PLL Lock Indicator Set by hardware when PLL is locked. Clear by hardware when PLL is unlocked.
3
PLLRES
2
-
1
PLLEN
0
PLOCK
Reset Value = 0000 1000b
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Table 18. PLLNDIV Register PLLNDIV (S:EEh) - PLL N Divider Register
7 Bit Number 7 6-0 6 N6 5 N5 4 N4 3 N3 2 N2 1 N1 0 N0
Bit Mnemonic Description N6:0 Reserved The value read from this bit is always 0. Do not set this bit. PLL N Divider 7 - bit N divider.
Reset Value = 0000 0000b Table 19. PLLRDIV Register PLLRDIV (S:EFh) - PLL R Divider Register
7 R9 Bit Number 7-0 6 R8 5 R7 4 R6 3 R5 2 R4 1 R3 0 R2
Bit Mnemonic Description R9:2 PLL Most Significant Bits R Divider 8 MSB of the 10-bit R divider.
Reset Value = 0000 0000b
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Program/Code Memory
The AT8xC51SND1C implement 64K Bytes of on-chip program/code memory. Figure 11 shows the split of internal and external program/code memory spaces depending on the product. The AT83C51SND1C product provides the internal program/code memory in ROM memory while the AT89C51SND1C product provides it in Flash memory. These 2 products do not allow external code memory execution. The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. The high voltage needed for programming or erasing Flash cells is generated on-chip using the standard V DD voltage, made possible by the internal charge pump. Thus, the AT89C51SND1C can be programmed using only one voltage and allows In-application software programming. Hardware programming mode is also available using common programming tools. See the application note `Programming T89C51x and AT89C51x with Device Programmers'. The AT89C51SND1C implements an additional 4K Bytes of on-chip boot Flash memory provided in Flash memory. This boot memory is delivered programmed with a standard boot loader software allowing In-System Programming (ISP). It also contains some Application Programming Interface routines named API routines allowing In Application Programming (IAP) by using user's own boot loader. Figure 11. Program/Code Memory Organization
FFFFh FFFFh F000h FFFFh F000h 4K Bytes Boot Flash
64K Bytes Code ROM
64K Bytes Code Flash
0000h
0000h
AT83C51SND1C
AT89C51SND1C
ROM Memory Architecture
As shown in Figure 11 the AT83C51SND1C ROM memory is composed of one space detailed in the following paragraphs.
Figure 12. AT83C51SND1C Memory Architecture
FFFFh
64K Bytes User ROM Memory
0000h
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User Space
This space is composed of a 64K Bytes ROM memory programmed during the manufacturing process. It contains the user's application code. As shown in Figure 13 the AT89C51SND1C Flash memory is composed of four spaces detailed in the following paragraphs.
Flash Memory Architecture
Figure 13. AT89C51SND1C Memory Architecture
Hardware Security Extra Row
FFFFh FFFFh
4K Bytes Flash Memory F000h
Boot
64K Bytes User Flash Memory
0000h
User Space
This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128 Bytes. It contains the user's application code. This space can be read or written by both software and hardware modes.
Boot Space
This space is composed of a 4K Bytes Flash memory. It contains the boot loader for InSystem Programming and the routines for In Application Programming. This space can only be read or written by hardware mode using a parallel programming tool.
Hardware Security Space
This space is composed of one Byte: the Hardware Security Byte (HSB see Table 22) divided in 2 separate nibbles. The MSN contains the X2 mode configuration bit and the Boot Loader Jump Bit as detailed in Section "Boot Memory Execution", page 19 and can be written by software while the LSN contains the lock system level to protect the memory content against piracy as detailed in Section "Hardware Security System", page 19 and can only be written by hardware. This space is composed of 2 Bytes: * * The Software Boot Vector (SBV, see Table 23). This Byte is used by the software boot loader to build the boot address. The Software Security Byte (SSB, see Table 24). This Byte is used to lock the execution of some boot loader commands.
Extra Row Space
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Hardware Security System
The AT89C51SND1C implements three lock bits LB2:0 in the LSN of HSB (see Table 22) providing three levels of security for user's program as described in Table 22 while the AT83C51SND1C is always set in read disabled mode. Level 0 is the level of an erased part and does not enable any security feature. Level 1 locks the hardware programming of both user and boot memories. Level 2 locks also hardware verifying of both user and boot memories Level 3 locks also the external execution. Table 20. Lock Bit Features(1)
Level LB2(2) 0 1 2 3(3) U U U P LB1 U U P X LB0 U P X X Internal Execution Enable Enable Enable Enable External Execution Enable Enable Enable Disable Hardware Verifying Enable Enable Disable Disable Hardware Software Programming Programming Enable Disable Disable Disable Enable Enable Enable Enable
Notes:
1. U means unprogrammed, P means programmed and X means don't care (programmed or unprogrammed). 2. LB2 is not implemented in the AT8xC51SND1C products. 3. AT89C51SND1C products are delivered with third level programmed to ensure that the code programmed by software using ISP or user's boot loader is secured from any hardware piracy.
Boot Memory Execution
As internal C51 code space is limited to 64K Bytes, some mechanisms are implemented to allow boot memory to be mapped in the code space for execution at addresses from F000h to FFFFh. The boot memory is enabled by setting the ENBOOT bit in AUXR1 (see Figure 21). The three ways to set this bit are detailed in the following sections. The software way to set ENBOOT consists in writing to AUXR1 from the user's software. This enables boot loader or API routines execution. The hardware condition is based on the ISP pin. When driving this pin to low level, the chip reset sets ENBOOT and forces the reset vector to F000h instead of 0000h in order to execute the boot loader software. As shown in Figure 14 the hardware condition always allows in-system recovery when user's memory has been corrupted.
Software Boot Mapping
Hardware Condition Boot Mapping
Programmed Condition Boot Mapping
The programmed condition is based on the Boot Loader Jump Bit (BLJB) in HSB. As shown in Figure 14 when this bit is programmed (by hardware or software programming mode), the chip reset set ENBOOT and forces the reset vector to F000h instead of 0000h, in order to execute the boot loader software.
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Figure 14. Hardware Boot Process Algorithm
RESET
Hard Cond?
ISP = L?
Hardware Process
Prog Cond? BLJB = P?
Hard Cond Init ENBOOT = 1 PC = F000h FCON = 00h
Standard Init ENBOOT = 0 PC = 0000h FCON = F0h
Prog Cond Init ENBOOT = 1 PC = F000h FCON = F0h
Software Process
User's Application
Atmel's Boot Loader
The software process (boot loader) is detailed in the "Boot Loader Datasheet" Document.
Preventing Flash Corruption
See Section "Reset Recommendation to Prevent Flash Corruption", page 47.
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Registers
Table 21. AUXR1 Register AUXR1 (S:A2h) - Auxiliary Register 1
7 Bit Number 7-6 6 5 ENBOOT 4 3 GF3 2 0 1 0 DPS
Bit Mnemonic Description Reserved The value read from these bits are indeterminate. Do not set these bits. Enable Boot Flash Set this bit to map the boot Flash in the code space between at addresses F000h to FFFFh. Clear this bit to disable boot Flash. Reserved The value read from this bit is indeterminate. Do not set this bit. General Flag This bit is a general-purpose user flag. Always Zero This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag. Reserved for Data Pointer Extension. Data Pointer Select Bit Set to select second data pointer: DPTR1. Clear to select first data pointer: DPTR0.
5
ENBOOT
1
4
-
3
GF3
2
0
1
-
0
DPS
Reset Value = XXXX 00X0b
Note: 1. ENBOOT bit is only available in AT89C51SND1C product.
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Hardware Bytes
Table 22. HSB Byte - Hardware Security Byte
7 X2B Bit Number 6 BLJB 5 4 3 2 LB2 1 LB1 0 LB0
Bit Mnemonic Description X2B(1) X2 Bit Program this bit to start in X2 mode. Unprogram (erase) this bit to start in standard mode. Boot Loader Jump Bit Program this bit to execute the boot loader at address F000h on next reset. Unprogram (erase) this bit to execute user's application at address 0000h on next reset. Reserved The value read from these bits is always unprogrammed. Do not program these bits. Reserved The value read from this bit is always unprogrammed. Do not program this bit. Hardware Lock Bits Refer to for bits description.
7
6
BLJB
(2)
5-4
-
3
-
2-0
LB2:0
Reset Value = XXUU UXXX, UUUU UUUU after an hardware full chip erase.
Note: 1. X2B initializes the X2 bit in CKCON during the reset phase. 2. In order to ensure boot loader activation at first power-up, AT89C51SND1C products are delivered with BLJB programmed. 3. Bits 0 to 3 (LSN) can only be programmed by hardware mode.
Table 23. SBV Byte - Software Boot Vector
7 ADD15 Bit Number 7-0 6 ADD14 5 ADD13 4 ADD12 3 ADD11 2 ADD10 1 ADD9 0 ADD8
Bit Mnemonic Description ADD15:8 MSB of the user's boot loader 16-bit address location Refer to the boot loader datasheet for usage information (boot loader dependent)
Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase. Table 24. SSB Byte - Software Security Byte
7 SSB7 Bit Number 7-0 6 SSB6 5 SSB5 4 SSB4 3 SSB3 2 SSB2 1 SSB1 0 SSB0
Bit Mnemonic Description SSB7:0 Software Security Byte Data Refer to the boot loader datasheet for usage information (boot loader dependent)
Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase.
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Data Memory
The AT8xC51SND1C provides data memory access in 2 different spaces: 1. The internal space mapped in three separate segments: - - - The lower 128 Bytes RAM segment The upper 128 Bytes RAM segment The expanded 2048 Bytes RAM segment
2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode. For information on this segment, refer to the Section "Special Function Registers", page 30. Figure 15 shows the internal and external data memory spaces organization. Figure 15. Internal and External Data Memory Organization
FFFFh
64K Bytes External XRAM 7FFh FFh Upper 128 Bytes Internal RAM Indirect Addressing 80h 7Fh 80h Lower 128 Bytes Internal RAM Direct or Indirect Addressing FFh Special Function Registers Direct Addressing
2K Bytes Internal ERAM EXTRAM = 0
0800h EXTRAM = 1 0000h
00h
00h
Internal Space
Lower 128 Bytes RAM The lower 128 Bytes of RAM (see Figure 16) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4 banks of 8 registers (R0 to R7). 2 bits RS0 and RS1 in PSW register (see Table 28) select which bank is in use according to Table 25. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing, and can be used for context switching in interrupt service routines. Table 25. Register Bank Selection
RS1 0 0 1 1 RS0 0 1 0 1 Description Register bank 0 from 00h to 07h Register bank 1 from 08h to 0Fh Register bank 2 from 10h to 17h Register bank 3 from 18h to 1Fh
The next 16 Bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00h to 7Fh.
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Figure 16. Lower 128 Bytes Internal RAM Organization
7Fh
30h 2Fh 20h 18h 10h 08h 00h 1Fh 17h 0Fh 07h 4 Banks of 8 Registers R0-R7 Bit-Addressable Space (Bit Addresses 0-7Fh)
Upper 128 Bytes RAM
The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. The on-chip 2K Bytes of expanded RAM (ERAM) are accessible from address 0000h to 07FFh using indirect addressing mode through MOVX instructions. In this address range, EXTRAM bit in AUXR register (see Table 29) is used to select the ERAM (default) or the XRAM. As shown in Figure 15 when EXTRAM = 0, the ERAM is selected and when EXTRAM = 1, the XRAM is selected (see Section "External Space"). The ERAM memory can be resized using XRS1:0 bits in AUXR register to dynamically increase external access to the XRAM space. Table 26 details the selected ERAM size and address range. Table 26. ERAM Size Selection
XRS1 0 0 1 1 XRS0 0 1 0 1 ERAM Size 256 Bytes 512 Bytes 1K Byte 2K Bytes Address 0 to 00FFh 0 to 01FFh 0 to 03FFh 0 to 07FFh
Expanded RAM
Note:
Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile memory cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly.
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External Space
Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD, WR, and ALE). Figure 17 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 27 describes the external memory interface signals. Figure 17. External Data Memory Interface Structure
AT8xC51SND1C P2 ALE P0 AD7:0 Latch A7:0 A7:0 D7:0 RD WR OE WR A15:8 RAM PERIPHERAL A15:8
Table 27. External Data Memory Interface Signals
Signal Name A15:8 Type O Description Address Lines Upper address lines for the external bus. Address/Data Lines Multiplexed lower address lines and data for the external memory. Address Latch Enable ALE signals indicates that valid address information are available on lines AD7:0. Read Read signal output to external data memory. Write Write signal output to external memory. Alternate Function P2.7:0
AD7:0
I/O
P0.7:0
ALE
O
-
RD
O
P3.7
WR
O
P3.6
Page Access Mode
The AT8xC51SND1C implement a feature called Page Access that disables the output of DPH on P2 when executing MOVX @DPTR instruction. Page Access is enable by setting the DPHDIS bit in AUXR register. Page Access is useful when application uses both ERAM and 256 Bytes of XRAM. In this case, software modifies intensively EXTRAM bit to select access to ERAM or XRAM and must save it if used in interrupt service routine. Page Access allows external access above 00FFh address without generating DPH on P2. Thus ERAM is accessed using MOVX @Ri or MOVX @DPTR with DPTR < 0100h, and XRAM is accessed using MOVX @DPTR with DPTR 0100h while keeping P2 for general I/O usage.
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External Bus Cycles
This section describes the bus cycles the AT8xC51SND1C executes to read (see Figure 18), and write data (see Figure 19) in the external data memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode, refer to the Section "X2 Feature", page 12. Slow peripherals can be accessed by stretching the read and write cycles. This is done using the M0 bit in AUXR register. Setting this bit changes the width of the RD and WR signals from 3 to 15 CPU clock periods. For simplicity, Figure 18 and Figure 19 depict the bus cycle waveforms in idealized form and do not provide precise timing information. For bus cycle timing parameters refer to the Section "AC Characteristics". Figure 18. External Data Read Waveforms
CPU Clock ALE
RD(1)
P0 P2 Notes:
P2
DPL or Ri
D7:0
DPH or P2(2),(3)
1. RD signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. 3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH.
Figure 19. External Data Write Waveforms
CPU Clock ALE
WR(1)
P0 P2
P2
DPL or Ri
D7:0
DPH or P2(2),(3)
Notes:
1. WR signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. 3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH.
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Dual Data Pointer
Description The AT8xC51SND1C implement a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Table 21) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 20). Figure 20. Dual Data Pointer Implementation
DPL0 DPL1
DPTR0 DPTR1
0
DPL
1
DPS DPH0 DPH1
0
AUXR1.0
DPTR
DPH
1
Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a "source" pointer and the other one as a "destination" pointer. Below is an example of block move implementation using the 2 pointers and coded in assembler. The latest C compiler also takes advantage of this feature by providing enhanced algorithm libraries. The INC instruction is a short (2 Bytes) and fast (6 CPU clocks) way to manipulate the DPS bit in the AUXR1 register. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry.
; ; ; ; ASCII block move using dual data pointers Modifies DPTR0, DPTR1, A and PSW Ends when encountering NULL character Note: DPS exits opposite of entry state unless an extra INC AUXR1 is added EQU 0A2h DPTR,#SOURCE AUXR1 DPTR,#DEST AUXR1 A,@DPTR DPTR AUXR1 @DPTR,A DPTR mv_loop ; ; ; ; ; ; ; ; ; ; address of SOURCE switch data pointers address of DEST switch data pointers get a Byte from SOURCE increment SOURCE address switch data pointers write the Byte to DEST increment DEST address check for NULL terminator
AUXR1 move:
mov inc mov mv_loop: inc movx inc inc movx inc jnz end_move:
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Registers
Table 28. PSW Register PSW (S:8Eh) - Program Status Word Register
7 CY Bit Number 7 6 AC 5 F0 4 RS1 3 RS0 2 OV 1 F1 0 P
Bit Mnemonic Description CY Carry Flag Carry out from bit 1 of ALU operands. Auxiliary Carry Flag Carry out from bit 1 of addition operands. User Definable Flag 0 Register Bank Select Bits Refer to Table 25 for bits description. Overflow Flag Overflow set by arithmetic operations. User Definable Flag 1 Parity Bit Set when ACC contains an odd number of 1's. Cleared when ACC contains an even number of 1's.
6 5 4-3
AC F0 RS1:0
2 1
OV F1
0
P
Reset Value = 0000 0000b
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Table 29. AUXR Register AUXR (S:8Eh) - Auxiliary Control Register
7 Bit Number 7 6 EXT16 5 M0 4 DPHDIS 3 XRS1 2 XRS0 1 EXTRAM 0 AO
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. External 16-bit Access Enable Bit Set to enable 16-bit access mode during MOVX instructions. Clear to disable 16-bit access mode and enable standard 8-bit access mode during MOVX instructions. External Memory Access Stretch Bit Set to stretch RD or WR signals duration to 15 CPU clock periods. Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods. DPH Disable Bit Set to disable DPH output on P2 when executing MOVX @DPTR instruction. Clear to enable DPH output on P2 when executing MOVX @DPTR instruction. Expanded RAM Size Bits Refer to Table 26 for ERAM size description. External RAM Enable Bit Set to select the external XRAM when executing MOVX @Ri or MOVX @DPTR instructions. Clear to select the internal expanded RAM when executing MOVX @Ri or MOVX @DPTR instructions. ALE Output Enable Bit Set to output the ALE signal only during MOVX instructions. Clear to output the ALE signal at a constant rate of FCPU/3.
6
EXT16
5
M0
4
DPHDIS
3-2
XRS1:0
1
EXTRAM
0
AO
Reset Value = X000 1101b
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Special Function Registers
The Special Function Registers (SFRs) of the AT8xC51SND1C derivatives fall into the categories detailed in Table 30 to Table 46. The relative addresses of these SFRs are provided together with their reset values in Table 47. In this table, the bit-addressable registers are identified by Note 1.
Table 30. C51 Core SFRs
Mnemonic Add Name ACC B PSW SP DPL DPH E0h Accumulator F0h B Register D0h Program Status Word 81h Stack Pointer 82h Data Pointer Low Byte 83h Data Pointer High Byte CY AC F0 RS1 RS0 OV F1 P 7 6 5 4 3 2 1 0
Table 31. System Management SFRs
Mnemonic Add Name PCON AUXR AUXR1 NVERS 87h Power Control 8Eh Auxiliary Register 0 A2h Auxiliary Register 1 FBh Version Number 7 SMOD1 NV7 6 SMOD0 EXT16 NV6 5 M0 ENBOOT(1) NV5 4 DPHDIS NV4 3 GF1 XRS1 GF3 NV3 2 GF0 XRS0 0 NV2 1 PD EXTRAM NV1 0 IDL AO DPS NV0
Note:
1. ENBOOT bit is only available in AT89C51SND1C product.
Table 32. PLL and System Clock SFRs
Mnemonic Add Name CKCON PLLCON PLLNDIV PLLRDIV 8Fh Clock Control E9h PLL Control EEh PLL N Divider EFh PLL R Divider 7 R1 R9 6 R0 N6 R8 5 N5 R7 4 N4 R6 3 PLLRES N3 R5 2 N2 R4 1 PLLEN N1 R3 0 X2 PLOCK N0 R2
Table 33. Interrupt SFRs
Mnemonic Add Name IEN0 IEN1 IPH0 IPL0 IPH1 IPL1 A8h Interrupt Enable Control 0 B1h Interrupt Enable Control 1 B7h Interrupt Priority Control High 0 B8h Interrupt Priority Control Low 0 B3h Interrupt Priority Control High 1 B2h Interrupt Priority Control Low 1 7 EA 6 EAUD EUSB IPHAUD IPLAUD IPHUSB IPLUSB 5 EMP3 IPHMP3 IPLMP3 4 ES EKB IPHS IPLS IPHKB IPLKB 3 ET1 EADC IPHT1 IPLT1 IPHADC IPLADC 2 EX1 ESPI IPHX1 IPLX1 IPHSPI IPLSPI 1 ET0 EI2C IPHT0 IPLT0 IPHI2C IPLI2C 0 EX0 EMMC IPHX0 IPLX0 IPHMMC IPLMMC
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Table 34. Port SFRs
Mnemonic Add Name P0 P1 P2 P3 P4 P5 80h 8-bit Port 0 90h 8-bit Port 1 A0h 8-bit Port 2 B0h 8-bit Port 3 C0h 8-bit Port 4 D8h 4-bit Port 5 7 6 5 4 3 2 1 0
Table 35. Flash Memory SFR
Mnemonic Add Name FCON
(1)
7 FPL3
6 FPL2
5 FPL1
4 FPL0
3 FPS
2 FMOD1
1 FMOD0
0 FBUSY
D1h Flash Control
Note:
1. FCON register is only available in AT89C51SND1C product.
Table 36. Timer SFRs
Mnemonic Add Name TCON TMOD TL0 TH0 TL1 TH1 WDTRST WDTPRG 88h Timer/Counter 0 and 1 Control 89h Timer/Counter 0 and 1 Modes 8Ah Timer/Counter 0 Low Byte 8Ch Timer/Counter 0 High Byte 8Bh Timer/Counter 1 Low Byte 8Dh Timer/Counter 1 High Byte A6h Watchdog Timer Reset A7h Watchdog Timer Program WTO2 WTO1 WTO0 7 TF1 GATE1 6 TR1 C/T1# 5 TF0 M11 4 TR0 M01 3 IE1 GATE0 2 IT1 C/T0# 1 IE0 M10 0 IT0 M00
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Table 37. MP3 Decoder SFRs
Mnemonic Add Name MP3CON MP3STA MP3STA1 MP3DAT MP3ANC MP3VOL MP3VOR MP3BAS MP3MED MP3TRE MP3CLK AAh MP3 Control C8h MP3 Status AFh MP3 Status 1 ACh MP3 Data ADh MP3 Ancillary Data 9Eh MP3 Audio Volume Control Left 9Fh MP3 Audio Volume Control Right B4h MP3 Audio Bass Control B5h MP3 Audio Medium Control B6h MP3 Audio Treble Control EBh MP3 Clock Divider 7 MPEN MPANC MPD7 AND7 6 MPBBST MPREQ MPD6 AND6 5 CRCEN ERRLAY MPD5 AND5 4 MSKANC ERRSYN MPFREQ MPD4 AND4 VOL4 VOR4 BAS4 MED4 TRE4 MPCD4 3 MSKREQ ERRCRC MPBREQ MPD3 AND3 VOL3 VOR3 BAS3 MED3 TRE3 MPCD3 2 MSKLAY MPFS1 MPD2 AND2 VOL2 VOR2 BAS2 MED2 TRE2 MPCD2 1 MSKSYN MPFS0 MPD1 AND1 VOL1 VOR1 BAS1 MED1 TRE1 MPCD1 0 MSKCRC MPVER MPD0 AND0 VOL0 VOR0 BAS0 MED0 TRE0 MPCD0
Table 38. Audio Interface SFRs
Mnemonic Add Name AUDCON0 AUDCON1 AUDSTA AUDDAT AUDCLK 9Ah Audio Control 0 9Bh Audio Control 1 9Ch Audio Status 9Dh Audio Data ECh Audio Clock Divider 7 JUST4 SRC SREQ AUD7 6 JUST3 DRQEN UDRN AUD6 5 JUST2 MSREQ AUBUSY AUD5 4 JUST1 MUDRN AUD4 AUCD4 3 JUST0 AUD3 AUCD3 2 POL DUP1 AUD2 AUCD2 1 DSIZ DUP0 AUD1 AUCD1 0 HLR AUDEN AUD0 AUCD0
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Table 39. USB Controller SFRs
Mnemonic Add Name USBCON USBADDR USBINT USBIEN UEPNUM BCh USB Global Control C6h USB Address BDh USB Global Interrupt BEh USB Global Interrupt Enable C7h USB Endpoint Number 7 USBE FEN EPEN DIR FDAT7 FNUM7 6 5 4 UADD4 EORINT 3 UPRSM UADD3 SOFINT ESOFINT DTGL STLCRC FDAT3 BYCT3 FNUM3 2 RMWUPE UADD2 EPDIR 1 CONFG UADD1 EPNUM1 0 FADDEN UADD0 SPINT ESPINT EPNUM0 SUSPCLK SDRMWUP UADD6 NAKIEN UADD5 WUPCPU
EWUPCPU EEORINT NAKOUT NAKIN TXRDY FDAT4 BYCT4 FNUM4 CRCERR -
UEPCONX D4h USB Endpoint X Control UEPSTAX UEPRST UEPINT UEPIEN UEPDATX UBYCTX UFNUML UFNUMH USBCLK CEh USB Endpoint X Status D5h USB Endpoint Reset F8h USB Endpoint Interrupt C2h USB Endpoint Interrupt Enable CFh USB Endpoint X FIFO Data E2h USB Endpoint X Byte Counter BAh USB Frame Number Low BBh USB Frame Number High EAh USB Clock Divider
EPTYPE1 EPTYPE0 TXCMP EP0RST EP0INT EP0INTE FDAT0 BYCT0 FNUM0 FNUM8 USBCD0
RXOUTB1 STALLRQ FDAT6 BYCT6 FNUM6 FDAT5 BYCT5 FNUM5 CRCOK -
RXSETUP RXOUTB0 EP2RST EP2INT EP2INTE FDAT2 BYCT2 FNUM2 FNUM10 EP1RST EP1INT EP1INTE FDAT1 BYCT1 FNUM1 FNUM9 USBCD1
Table 40. MMC Controller SFRs
Mnemonic Add Name MMCON0 MMCON1 MMCON2 MMSTA MMINT MMMSK MMCMD MMDAT MMCLK E4h MMC Control 0 E5h MMC Control 1 E6h MMC Control 2 DEh MMC Control and Status E7h MMC Interrupt DFh MMC Interrupt Mask DDh MMC Command DCh MMC Data EDh MMC Clock Divider 7 DRPTR BLEN3 MMCEN MCBI MCBM MC7 MD7 MMCD7 6 DTPTR BLEN2 DCR EORI EORM MC6 MD6 MMCD6 5 CRPTR BLEN1 CCR CBUSY EOCI EOCM MC5 MD5 MMCD5 4 CTPTR BLEN0 CRC16S EOFI EOFM MC4 MD4 MMCD4 3 MBLOCK DATDIR DATFS F2FI F2FM MC3 MD3 MMCD3 2 DFMT DATEN DATD1 CRC7S F1FI F1FM MC2 MD2 MMCD2 1 RFMT RESPEN DATD0 RESPFS F2EI F2EM MC1 MD1 MMCD1 0 CRCDIS CMDEN FLOWC CFLCK F1EI F1EM MC0 MD0 MMCD0
Table 41. IDE Interface SFR
Mnemonic Add Name DAT16H F9h High Order Data Byte 7 D15 6 D14 5 D13 4 D12 3 D11 2 D10 1 D9 0 D8
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Table 42. Serial I/O Port SFRs
Mnemonic Add Name SCON SBUF SADEN SADDR BDRCON BRL 98h Serial Control 99h Serial Data Buffer B9h Slave Address Mask A9h Slave Address 92h Baud Rate Control 91h Baud Rate Reload BRR TBCK RBCK SPD SRC 7 FE/SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Table 43. SPI Controller SFRs
Mnemonic Add Name SPCON SPSTA SPDAT C3h SPI Control C4h SPI Status C5h SPI Data 7 SPR2 SPIF SPD7 6 SPEN WCOL SPD6 5 SSDIS SPD5 4 MSTR MODF SPD4 3 CPOL SPD3 2 CPHA SPD2 1 SPR1 SPD1 0 SPR0 SPD0
Table 44. Two Wire Controller SFRs
Mnemonic Add Name SSCON SSSTA SSDAT SSADR 93h Synchronous Serial Control 94h Synchronous Serial Status 95h Synchronous Serial Data 96h Synchronous Serial Address 7 SSCR2 SSC4 SSD7 SSA7 6 SSPE SSC3 SSD6 SSA6 5 SSSTA SSC2 SSD5 SSA5 4 SSSTO SSC1 SSD4 SSA4 3 SSI SSC0 SSD3 SSA3 2 SSAA 0 SSD2 SSA2 1 SSCR1 0 SSD1 SSA1 0 SSCR0 0 SSD0 SSGC
Table 45. Keyboard Interface SFRs
Mnemonic Add Name KBCON KBSTA A3h Keyboard Control A4h Keyboard Status 7 KINL3 KPDE 6 KINL2 5 KINL1 4 KINL0 3 KINM3 KINF3 2 KINM2 KINF2 1 KINM1 KINF1 0 KINM0 KINF0
Table 46. A/D Controller SFRs
Mnemonic Add Name ADCON ADCLK ADDL ADDH F3h ADC Control F2h ADC Clock Divider F4h ADC Data Low Byte F5h ADC Data High Byte 7 ADAT9 6 ADIDL ADAT8 5 ADEN ADAT7 4 ADEOC ADCD4 ADAT6 3 ADSST ADCD3 ADAT5 2 ADCD2 ADAT4 1 ADCD1 ADAT1 ADAT3 0 ADCS ADCD0 ADAT0 ADAT2
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AT8xC51SND1C
Table 47. SFR Addresses and Reset Values
0/8 F8h UEPINT 0000 0000 B(1) 0000 0000 PLLCON 0000 1000 ACC(1) 0000 0000 P5(1) XXXX 1111 PSW(1) 0000 0000 MP3STA(1) 0000 0001 P4(1) 1111 1111 IPL0(1) X000 0000 P3(1) 1111 1111 IEN0(1) 0000 0000 P2(1) 1111 1111 SCON 0000 0000 P1(1) 1111 1111 TCON(1) 0000 0000 P0(1) 1111 1111 0/8 SBUF XXXX XXXX BRL 0000 0000 TMOD 0000 0000 SP 0000 0111 1/9 SADEN 0000 0000 IEN1 0000 0000 SADDR 0000 0000 UEPIEN 0000 0000 UFNUML 0000 0000 IPL1 0000 0000 MP3CON 0011 1111 AUXR1 XXXX 00X0 AUDCON0 0000 1000 BDRCON XXX0 0000 TL0 0000 0000 DPL 0000 0000 2/A KBCON 0000 1111 AUDCON1 1011 0010 SSCON 0000 0000 TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E SPCON 0001 0100 UFNUMH 0000 0000 IPH1 0000 0000 SPSTA 0000 0000 USBCON 0000 0000 MP3BAS 0000 0000 MP3DAT 0000 0000 KBSTA 0000 0000 AUDSTA 1100 0000 SSSTA 1111 1000 TH0 0000 0000 AUDDAT 1111 1111 SSDAT 1111 1111 TH1 0000 0000 SPDAT XXXX XXXX USBINT 0000 0000 MP3MED 0000 0000 MP3ANC 0000 0000 WDTRST XXX XXXX MP3VOL 0000 0000 SSADR 1111 1110 AUXR X000 1101 CKCON 0000 000X(5) PCON XXXX 0000 7/F FCON(3) 1111 0000(4) 1/9 DAT16H XXXX XXXX ADCLK 0000 0000 USBCLK 0000 0000 UBYCTLX 0000 0000 2/A 3/B NVERS XXXX XXXX(2) ADCON 0000 0000 MP3CLK 0000 0000 ADDL 0000 0000 AUDCLK 0000 0000 MMCON0 0000 0000 MMDAT 1111 1111 UEPCONX 1000 0000 ADDH 0000 0000 MMCLK 0000 0000 MMCON1 0000 0000 MMCMD 1111 1111 UEPRST 0000 0000 UEPSTAX 0000 0000 USBADDR 0000 0000 USBIEN 0001 0000 MP3TRE 0000 0000 IPH0 X000 0000 MP3STA1 0100 0001 WDTPRG XXXX X000 MP3VOR 0000 0000 UEPDATX XXXX XXXX UEPNUM 0000 0000 PLLNDIV 0000 0000 MMCON2 0000 0000 MMSTA 0000 0000 PLLRDIV 0000 0000 MMINT 0000 0011 MMMSK 1111 1111 4/C 5/D 6/E 7/F FFh
F0h
F7h
E8h
EFh
E0h
E7h
D8h
DFh
D0h
D7h
C8h
CFh
C0h
C7h
B8h
BFh
B0h
B7h
A8h
AFh
A0h
A7h
98h
9Fh
90h
97h
88h
8Fh
80h
87h
Reserved
Notes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable. 2. NVERS reset value depends on the silicon version: 1000 0100 for AT89C51SND1C product and 0000 0001 for AT83C51SND1C product. 3. FCON register is only available in AT89C51SND1C product. 4. FCON reset value is 00h in case of reset with hardware condition. 5. CKCON reset value depends on the X2B bit (programmed or unprogrammed) in the Hardware Byte.
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Interrupt System
The AT8xC51SND1C, like other control-oriented computer architectures, employ a program interrupt method. This operation branches to a subroutine and performs some service in response to the interrupt. When the subroutine completes, execution resumes at the point where the interrupt occurred. Interrupts may occur as a result of internal AT8xC51SND1C activity (e.g., timer overflow) or at the initiation of electrical signals external to the microcontroller (e.g., keyboard). In all cases, interrupt operation is programmed by the system designer, who determines priority of interrupt service relative to normal code execution and other interrupt service routines. All of the interrupt sources are enabled or disabled by the system designer and may be manipulated dynamically. A typical interrupt event chain occurs as follows: * * * An internal or external device initiates an interrupt-request signal. The AT8xC51SND1C, latches this event into a flag buffer. The priority of the flag is compared to the priority of other interrupts by the interrupt handler. A high priority causes the handler to set an interrupt flag. This signals the instruction execution unit to execute a context switch. This context switch breaks the current flow of instruction sequences. The execution unit completes the current instruction prior to a save of the program counter (PC) and reloads the PC with the start address of a software service routine. The software service routine executes assigned tasks and as a final activity performs a RETI (return from interrupt) instruction. This instruction signals completion of the interrupt, resets the interrupt-in-progress priority and reloads the program counter. Program operation then continues from the original point of interruption.
*
Table 48. Interrupt System Signals
Signal Name INT0 Type I Description External Interrupt 0 See section "External Interrupts", page 39. External Interrupt 1 See section "External Interrupts", page 39. Keyboard Interrupt Inputs See section "Keyboard Interface", page 179. Alternate Function P3.2
INT1
I
P3.3
KIN3:0
I
P1.3:0
Six interrupt registers are used to control the interrupt system. 2 8-bit registers are used to enable separately the interrupt sources: IEN0 and IEN1 registers (see Table 51 and Table 52). Four 8-bit registers are used to establish the priority level of the thirteen sources: IPH0, IPL0, IPH1 and IPL1 registers (see Table 53 to Table 56).
Interrupt System Priorities
Each of the thirteen interrupt sources on the AT8xC51SND1C can be individually programmed to one of four priority levels. This is accomplished by one bit in the Interrupt Priority High registers (IPH0 and IPH1) and one bit in the Interrupt Priority Low registers (IPL0 and IPL1). This provides each interrupt source four possible priority levels according to Table 49.
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Table 49. Priority Levels
IPHxx 0 0 1 1 IPLxx 0 1 0 1 Priority Level 0 Lowest 1 2 3 Highest
A low-priority interrupt is always interrupted by a higher priority interrupt but not by another interrupt of lower or equal priority. Higher priority interrupts are serviced before lower priority interrupts. The response to simultaneous occurrence of equal priority interrupts is determined by an internal hardware polling sequence detailed in Table 50. Thus, within each priority level there is a second priority structure determined by the polling sequence. The interrupt control system is shown in Figure 21. Table 50. Priority within Same Level
Interrupt Address Vectors C:0003h C:000Bh C:0013h C:001Bh C:0023h C:002Bh C:0033h C:003Bh C:0043h C:004Bh C:0053h C:005Bh C:0063h C:006Bh C:0073h Interrupt Request Flag Cleared by Hardware (H) or by Software (S) H if edge, S if level H H if edge, S if level H S S S S S S S S S -
Interrupt Name INT0 Timer 0 INT1 Timer 1 Serial Port MP3 Decoder Audio Interface MMC Interface Two Wire Controller SPI Controller A to D Converter Keyboard Reserved USB Reserved
Priority Number 1 (Highest Priority) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Lowest Priority)
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Figure 21. Interrupt Control System INT0
External Interrupt 0 EX0
IEN0.0
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
Highest Priority Interrupts
Timer 0 ET0 INT1 External Interrupt 1
IEN0.1
EX1
IEN0.2
Timer 1 ET1 TXD RXD Serial Port
IEN0.3
ES MP3 Decoder
IEN0.4
EMP3 Audio Interface MCLK MDAT MCMD SCL SDA SCK SI SO
IEN0.5
EAUD MMC Controller
IEN0.6
EMMC TWI Controller
IEN1.0
EI2C SPI Controller
IEN1.1
ESPI AIN1:0 A to D Converter
IEN1.2
EADC
IEN1.3
KIN3:0
Keyboard EKB
D+ D-
USB Controller
IEN1.4
EUSB
IEN1.6
EA
IEN0.7
Interrupt Enable
IPH/L Priority Enable
Lowest Priority Interrupts
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External Interrupts
INT1:0 Inputs External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to be level-triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in TCON register as shown in Figure 22. If ITn = 0, INTn is triggered by a low level at the pin. If ITn = 1, INTn is negative-edge triggered. External interrupts are enabled with bits EX0 and EX1 (EXn, n = 0 or 1) in IEN0. Events on INTn set the interrupt request flag IEn in TCON register. If the interrupt is edge-triggered, the request flag is cleared by hardware when vectoring to the interrupt service routine. If the interrupt is level-triggered, the interrupt service routine must clear the request flag and the interrupt must be deasserted before the end of the interrupt service routine. INT0 and INT1 inputs provide both the capability to exit from Power-down mode on low level signals as detailed in section "Exiting Power-down Mode", page 48. Figure 22. INT1:0 Input Circuitry
INT0/1
0
IE0/1
1
TCON.1/3
INT0/1 Interrupt Request EX0/1
IEN0.0/2
IT0/1
TCON.0/2
KIN3:0 Inputs
External interrupts KIN0 to KIN3 provide the capability to connect a matrix keyboard. For detailed information on these inputs, refer to section "Keyboard Interface", page 179. External interrupt pins (INT1:0 and KIN3:0) are sampled once per peripheral cycle (6 peripheral clock periods) (see Figure 23). A level-triggered interrupt pin held low or high for more than 6 peripheral clock periods (12 oscillator in standard mode or 6 oscillator clock periods in X2 mode) guarantees detection. Edge-triggered external interrupts must hold the request pin low for at least 6 peripheral clock periods. Figure 23. Minimum Pulse Timings
Level-Triggered Interrupt > 1 Peripheral Cycle
Input Sampling
1 cycle Edge-Triggered Interrupt > 1 Peripheral Cycle
1 cycle
1 cycle
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Registers
Table 51. IEN0 Register IEN0 (S:A8h) - Interrupt Enable Register 0
7 EA Bit Number 6 EAUD 5 EMP3 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
Bit Mnemonic Description Enable All Interrupt Bit Set to enable all interrupts. Clear to disable all interrupts. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. Audio Interface Interrupt Enable Bit Set to enable audio interface interrupt. Clear to disable audio interface interrupt. MP3 Decoder Interrupt Enable Bit Set to enable MP3 decoder interrupt. Clear to disable MP3 decoder interrupt. Serial Port Interrupt Enable Bit Set to enable serial port interrupt. Clear to disable serial port interrupt. Timer 1 Overflow Interrupt Enable Bit Set to enable timer 1 overflow interrupt. Clear to disable timer 1 overflow interrupt. External Interrupt 1 Enable bit Set to enable external interrupt 1. Clear to disable external interrupt 1. Timer 0 Overflow Interrupt Enable Bit Set to enable timer 0 overflow interrupt. Clear to disable timer 0 overflow interrupt. External Interrupt 0 Enable Bit Set to enable external interrupt 0. Clear to disable external interrupt 0.
7
EA
6
EAUD
5
EMP3
4
ES
3
ET1
2
EX1
1
ET0
0
EX0
Reset Value = 0000 0000b
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Table 52. IEN1 Register IEN1 (S:B1h) - Interrupt Enable Register 1
7 Bit Number 7 6 EUSB 5 4 EKB 3 EADC 2 ESPI 1 EI2C 0 EMMC
Bit Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. USB Interface Interrupt Enable Bit Set this bit to enable USB interrupts. Clear this bit to disable USB interrupts. Reserved The value read from this bit is always 0. Do not set this bit. Keyboard Interface Interrupt Enable Bit Set to enable Keyboard interrupt. Clear to disable Keyboard interrupt. A to D Converter Interrupt Enable Bit Set to enable ADC interrupt. Clear to disable ADC interrupt. SPI Controller Interrupt Enable Bit Set to enable SPI interrupt. Clear to disable SPI interrupt. Two Wire Controller Interrupt Enable Bit Set to enable Two Wire interrupt. Clear to disable Two Wire interrupt. MMC Interface Interrupt Enable Bit Set to enable MMC interrupt. Clear to disable MMC interrupt.
6
EUSB
5
-
4
EKB
3
EADC
2
ESPI
1
EI2C
0
EMMC
Reset Value = 0000 0000b
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Table 53. IPH0 Register IPH0 (S:B7h) - Interrupt Priority High Register 0
7 Bit Number 7 6 IPHAUD 5 IPHMP3 4 IPHS 3 IPHT1 2 IPHX1 1 IPHT0 0 IPHX0
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Audio Interface Interrupt Priority Level MSB Refer to Table 49 for priority level description. MP3 Decoder Interrupt Priority Level MSB Refer to Table 49 for priority level description. Serial Port Interrupt Priority Level MSB Refer to Table 49 for priority level description. Timer 1 Interrupt Priority Level MSB Refer to Table 49 for priority level description. External Interrupt 1 Priority Level MSB Refer to Table 49 for priority level description. Timer 0 Interrupt Priority Level MSB Refer to Table 49 for priority level description. External Interrupt 0 Priority Level MSB Refer to Table 49 for priority level description.
6
IPHAUD
5
IPHMP3
4
IPHS
3
IPHT1
2
IPHX1
1
IPHT0
0
IPHX0
Reset Value = X000 0000b
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Table 54. IPH1 Register IPH1 (S:B3h) - Interrupt Priority High Register 1
7 Bit Number 7 6 IPHUSB 5 4 IPHKB 3 IPHADC 2 IPHSPI 1 IPHI2C 0 IPHMMC
Bit Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. USB Interrupt Priority Level MSB Refer to Table 49 for priority level description. Reserved The value read from this bit is always 0. Do not set this bit. Keyboard Interrupt Priority Level MSB Refer to Table 49 for priority level description. A to D Converter Interrupt Priority Level MSB Refer to Table 49 for priority level description. SPI Interrupt Priority Level MSB Refer to Table 49 for priority level description. Two Wire Controller Interrupt Priority Level MSB Refer to Table 49 for priority level description. MMC Interrupt Priority Level MSB Refer to Table 49 for priority level description.
6
IPHUSB
5
-
4
IPHKB
3
IPHADC
2
IPHSPI
1
IPHI2C
0
IPHMMC
Reset Value = 0000 0000b
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Table 55. IPL0 Register IPL0 (S:B8h) - Interrupt Priority Low Register 0
7 Bit Number 7 6 IPLAUD 5 IPLMP3 4 IPLS 3 IPLT1 2 IPLX1 1 IPLT0 0 IPLX0
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Audio Interface Interrupt Priority Level LSB Refer to Table 49 for priority level description. MP3 Decoder Interrupt Priority Level LSB Refer to Table 49 for priority level description. Serial Port Interrupt Priority Level LSB Refer to Table 49 for priority level description. Timer 1 Interrupt Priority Level LSB Refer to Table 49 for priority level description. External Interrupt 1 Priority Level LSB Refer to Table 49 for priority level description. Timer 0 Interrupt Priority Level LSB Refer to Table 49 for priority level description. External Interrupt 0 Priority Level LSB Refer to Table 49 for priority level description.
6
IPLAUD
5
IPLMP3
4
IPLS
3
IPLT1
2
IPLX1
1
IPLT0
0
IPLX0
Reset Value = X000 0000b
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Table 56. IPL1 Register IPL1 (S:B2h) - Interrupt Priority Low Register 1
7 Bit Number 7 6 IPLUSB 5 4 IPLKB 3 IPLADC 2 IPLSPI 1 IPLI2C 0 IPLMMC
Bit Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. USB Interrupt Priority Level LSB Refer to Table 49 for priority level description. Reserved The value read from this bit is always 0. Do not set this bit. Keyboard Interrupt Priority Level LSB Refer to Table 49 for priority level description. A to D Converter Interrupt Priority Level LSB Refer to Table 49 for priority level description. SPI Interrupt Priority Level LSB Refer to Table 49 for priority level description. Two Wire Controller Interrupt Priority Level LSB Refer to Table 49 for priority level description. MMC Interrupt Priority Level LSB Refer to Table 49 for priority level description.
6
IPLUSB
5
-
4
IPLKB
3
IPLADC
2
IPLSPI
1
IPLI2C
0
IPLMMC
Reset Value = 0000 0000b
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Power Management
2 power reduction modes are implemented in the AT8xC51SND1C: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in section "X2 Feature", page 12. In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an high level has to be applied on the RST pin. A bad level leads to a wrong initialization of the internal registers like SFRs, Program Counter... and to unpredictable behavior of the microcontroller. A proper device reset initializes the AT8xC51SND1C and vectors the CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to VDD as shown in Figure 24. A warm reset can be applied either directly on the RST pin or indirectly by an internal reset source such as the watchdog timer. Resistor value and input characteristics are discussed in the Section "DC Characteristics" of the AT8xC51SND1C datasheet. The status of the Port pins during reset is detailed in Table 57. Figure 24. Reset Circuitry and Power-On Reset
VDD
Reset
From Internal Reset Source To CPU Core and Peripherals
VDD
P
RST
RRST
+
RST
VSS
RST input circuitry
Power-on Reset
Table 57. Pin Conditions in Special Operating Modes
Mode Reset Idle Power-down Port 0 Floating Data Data Port 1 High Data Data Port 2 High Data Data Port 3 High Data Data Port 4 High Data Data Port 5 High Data Data MMC Floating Data Data Audio
1
Data Data
Note:
1. Refer to section "Audio Output Interface", page 73.
Cold Reset
2 conditions are required before enabling a CPU start-up: * * VDD must reach the specified VDD range The level on X1 input pin must be outside the specification (VIH, VIL)
If one of these 2 conditions are not met, the microcontroller does not start correctly and can execute an instruction fetch from anywhere in the program space. An active level applied on the RST pin must be maintained till both of the above conditions are met. A reset is active when the level V IH1 is reached and when the pulse width covers the period of time where VDD and the oscillator are not stabilized. 2 parameters have to be taken into account to determine the reset pulse width: * * VDD rise time, Oscillator startup time.
To determine the capacitor value to implement, the highest value of these 2 parameters has to be chosen. Table 58 gives some capacitor values examples for a minimum RRST of 50 K and different oscillator startup and VDD rise times.
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Table 58. Minimum Reset Capacitor Value for a 50 k Pull-down Resistor(1)
Oscillator Start-Up Time 5 ms 20 ms Note: VDD Rise Time 1 ms 820 nF 2.7 F 10 ms 1.2 F 3.9 F 100 ms 12 F 12 F
1. These values assume VDD starts from 0V to the nominal value. If the time between 2 on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully discharged, leading to a bad reset sequence.
Warm Reset
To achieve a valid reset, the reset signal must be maintained for at least 2 machine cycles (24 oscillator clock periods) while the oscillator is running. The number of clock periods is mode independent (X2 or X1). As detailed in section "Watchdog Timer", page 59, the WDT generates a 96-clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1 k resistor must be added as shown in Figure 25. Figure 25. Reset Circuitry for WDT Reset-out Usage
VDD
Watchdog Reset
+
VDD
From WDT Reset Source To CPU Core and Peripherals
RST
VDD
1K
P
RST
RRST
VSS
VSS
To Other On-board Circuitry
Reset Recommendation to Prevent Flash Corruption
An example of bad initialization situation may occur in an instance where the bit ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since this bit allows mapping of the bootloader in the code area, a reset failure can be critical. If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet due to a bad reset) the bit ENBOOT in SFRs may be set. If the value of Program Counter is accidently in the range of the boot memory addresses then a Flash access (write or erase) may corrupt the Flash on-chip memory. It is recommended to use an external reset circuitry featuring power supply monitoring to prevent system malfunction during periods of insufficient power supply voltage (power supply failure, power supply switched off).
Idle Mode
Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked (refer to section "Oscillator", page 12). The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during Idle mode is detailed in Table 57.
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Entering Idle Mode
To enter Idle mode, the user must set the IDL bit in PCON register (see Table 59). The AT8xC51SND1C enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed.
Note: If IDL bit and PD bit are set simultaneously, the AT8xC51SND1C enter Power-down mode. Then it does not go in Idle mode when exiting Power-down mode.
Exiting Idle Mode
There are 2 ways to exit Idle mode: 1. Generate an enabled interrupt. - Hardware clears IDL bit in PCON register which restores the clock to the CPU. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode. The general-purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. A logic high on the RST pin clears IDL bit in PCON register directly and asynchronously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT8xC51SND1C and vectors the CPU to address C:0000h.
During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM.
2. Generate a reset. -
Note:
Power-down Mode
The Power-down mode places the AT8xC51SND1C in a very low power state. Powerdown mode stops the oscillator and freezes all clocks at known states (refer to the Section "Oscillator", page 12). The CPU status prior to entering Power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-down mode. In addition, the SFRs and RAM contents are preserved. The status of the Port pins during Power-down mode is detailed in Table 57.
Note: VDD may be reduced to as low as VRET during Power-down mode to further reduce power dissipation. Notice, however, that VDD is not reduced until Power-down mode is invoked.
Entering Power-down Mode
To enter Power-down mode, set PD bit in PCON register. The AT8xC51SND1C enters the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. If VDD was reduced during the Power-down mode, do not exit Power-down mode until VDD is restored to the normal operating level. There are 2 ways to exit the Power-down mode: 1. Generate an enabled external interrupt. - The AT8xC51SND1C provides capability to exit from Power-down using INT0, INT1, and KIN3:0 inputs. In addition, using KIN input provides high or low level exit capability (see section "Keyboard Interface", page 179). Hardware clears PD bit in PCON register which starts the oscillator and restores the clocks to the CPU and peripherals. Using INTn input, execution
Exiting Power-down Mode
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resumes when the input is released (see Figure 26) while using KINx input, execution resumes after counting 1024 clock ensuring the oscillator is restarted properly (see Figure 27). This behavior is necessary for decoding the key while it is still pressed. In both cases, execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-down mode.
Note: 1. The external interrupt used to exit Power-down mode must be configured as level sensitive (INT0 and INT1) and must be assigned the highest priority. In addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted. 2. Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM content.
Figure 26. Power-down Exit Waveform Using INT1:0
INT1:0
OSC
Active phase
Power-down Phase
Oscillator Restart Phase
Active Phase
Figure 27. Power-down Exit Waveform Using KIN3:0
KIN3:01
OSC
Active phase
Power-down Phase
1024 clock count
Active phase
Note:
1. KIN3:0 can be high or low-level triggered.
2. Generate a reset. - A logic high on the RST pin clears PD bit in PCON register directly and asynchronously. This starts the oscillator and restores the clock to the CPU and peripherals. Program execution momentarily resumes with the instruction immediately following the instruction that activated Power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT8xC51SND1C and vectors the CPU to address 0000h.
1. During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated the Power-down mode should not write to a Port pin or to the external RAM. 2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal RAM content.
Notes:
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Registers
Table 59. PCON Register PCON (S:87h) - Power Configuration Register
7 Bit Number 7-4 6 5 4 3 GF1 2 GF0 1 PD 0 IDL
Bit Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set these bits. General-purpose flag 1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. General-purpose flag 0 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. Power-down Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-down mode. If IDL and PD are both set, PD takes precedence. Idle Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.
3
GF1
2
GF0
1
PD
0
IDL
Reset Value = XXXX 0000b
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Timers/Counters
The AT8xC51SND1C implement 2 general-purpose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various operating modes of each Timer/Counter are described in the following sections.
Timer/Counter Operations
For instance, a basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Table 60) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise, the behavior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is FPER/6, i.e., FOSC/12 in standard mode or FOSC/6 in X2 mode. For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on the Tx external input pin. The external input is sampled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is FPER/12, i.e., FOSC/24 in standard mode or FOSC/12 in X2 mode. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle.
Timer Clock Controller
As shown in Figure 28, the Timer 0 (FT0) and Timer 1 (FT1) clocks are derived from either the peripheral clock (FPER) or the oscillator clock (FOSC) depending on the T0X2 and T1X2 bits in CKCON register. These clocks are issued from the Clock Controller block as detailed in Section "Clock Controller", page 12. When T0X2 or T1X2 bit is set, the Timer 0 or Timer 1 clock frequency is fixed and equal to the oscillator clock frequency divided by 2. When cleared, the Timer clock frequency is equal to the oscillator clock frequency divided by 2 in standard mode or to the oscillator clock frequency in X2 mode.
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Figure 28. Timer 0 and Timer 1 Clock Controller and Symbols
PER CLOCK OSC CLOCK 0
Timer 0 Clock
1
PER CLOCK OSC CLOCK
0
Timer 1 Clock
1
/2 T0X2
CKCON.1
/2 T1X2
CKCON.2
TIM0 CLOCK
TIM1 CLOCK
Timer 0 Clock Symbol
Timer 1 Clock Symbol
Timer 0
Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 29 through Figure 35 show the logical configuration of each mode. Timer 0 is controlled by the four lower bits of TMOD register (see Table 61) and bits 0, 1, 4 and 5 of TCON register (see Table 60). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (C/T0#) and mode of operation (M10 and M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0 to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an interrupt request. It is important to stop Timer/Counter before changing mode.
Mode 0 (13-bit Timer)
Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (see Figure 29). The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register. Figure 30 gives the overflow period calculation formula.
Figure 29. Timer/Counter x (x = 0 or 1) in Mode 0
TIMx CLOCK Tx C/Tx# TMOD Reg INTx GATEx TMOD Reg /6 0 1 TLx (5 Bits) THx (8 Bits) Overflow Timer x Interrupt Request
TFx TCON reg
TRx TCON Reg
Figure 30. Mode 0 Overflow Period Formula
TFxPER=
6 (16384 - (THx, TLx))
FTIMx
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Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 31). The selected input increments TL0 register. Figure 32 gives the overflow period calculation formula when in timer mode.
Figure 31. Timer/Counter x (x = 0 or 1) in Mode 1
TIMx CLOCK /6 0 1
THx (8 bits)
TLx (8 bits)
Overflow
TFx
TCON Reg
Tx C/Tx#
TMOD Reg
Timer x Interrupt Request
INTx GATEx
TMOD Reg
TRx
TCON Reg
Figure 32. Mode 1 Overflow Period Formula
TFxPER= 6 (65536 - (THx, TLx)) FTIMx
Mode 2 (8-bit Timer with AutoReload)
Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads from TH0 register (see Table 62). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any time by writing it to TH0 register. Figure 34 gives the autoreload period calculation formula when in timer mode.
Figure 33. Timer/Counter x (x = 0 or 1) in Mode 2
TIMx CLOCK /6 0 1
TLx (8 bits)
Overflow
TFx
TCON reg
Tx C/Tx#
TMOD reg
Timer x Interrupt Request
INTx GATEx
TMOD reg
TRx
TCON reg
THx (8 bits)
Figure 34. Mode 2 Autoreload Period Formula
TFxPER= 6 (256 - THx) FTIMx
Mode 3 (2 8-bit Timers)
Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers (see Figure 35). This mode is provided for applications requiring an additional 8bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD register, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a Timer function (counting FTF1/6) and takes over use of the Timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode
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3. Figure 34 gives the autoreload period calculation formulas for both TF0 and TF1 flags. Figure 35. Timer/Counter 0 in Mode 3: 2 8-bit Counters
TIM0 CLOCK /6 0 1
TL0 (8 bits)
Overflow
TF0
TCON.5
T0 C/T0#
TMOD.2
Timer 0 Interrupt Request
INT0
GATE0
TMOD.3
TR0
TCON.4
TIM0 CLOCK
/6
TH0 (8 bits) TR1
TCON.6
Overflow
TF1
TCON.7
Timer 1 Interrupt Request
Figure 36. Mode 3 Overflow Period Formula
TF0PER = 6 (256 - TL0) FTIM0 TF1PER = 6 (256 - TH0) FTIM0
Timer 1
Timer 1 is identical to Timer 0 except for Mode 3 which is a hold-count mode. The following comments help to understand the differences: * Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 29 through Figure 33 show the logical configuration for modes 0, 1, and 2. Timer 1's mode 3 is a hold-count mode. Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 61) and bits 2, 3, 6 and 7 of TCON register (see Figure 60). TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01). TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1). Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose. For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1 to control Timer operation. Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request. When Timer 0 is in mode 3, it uses Timer 1's overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on. It is important to stop the Timer/Counter before changing modes.
*
* *
* *
*
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Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 29). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments TH1 register. Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 31). The selected input increments TL1 register. Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 register on overflow (see Figure 33). TL1 overflow sets TF1 flag in TCON register and reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3. Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register.
Mode 1 (16-bit Timer)
Mode 2 (8-bit Timer with AutoReload)
Mode 3 (Halt)
Interrupt
Figure 37. Timer Interrupt System
TF0
TCON.5
Timer 0 Interrupt Request ET0
IEN0.1
TF1
TCON.7
Timer 1 Interrupt Request ET1
IEN0.3
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Registers
Table 60. TCON Register TCON (S:88h) - Timer/Counter Control Register
7 TF1 Bit Number 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0
Bit Mnemonic Description Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. Timer 0 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows. Timer 0 Run Control Bit Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. Interrupt 1 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT1). Set by hardware when external interrupt is detected on INT1 pin. Interrupt 1 Type Control Bit Clear to select low level active (level triggered) for external interrupt 1 (INT1). Set to select falling edge active (edge triggered) for external interrupt 1. Interrupt 0 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0 pin. Interrupt 0 Type Control Bit Clear to select low level active (level triggered) for external interrupt 0 (INT0). Set to select falling edge active (edge triggered) for external interrupt 0.
7
TF1
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Reset Value = 0000 0000b
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Table 61. TMOD Register TMOD (S:89h) - Timer/Counter Mode Control Register
7 GATE1 6 C/T1# 5 M11 4 M01 3 GATE0 2 C/T0# 1 M10 0 M00
Bit Bit Number Mnemonic Description Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set. Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. Timer 1 Mode Select Bits Operating mode M11 M01 0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). 0 1 Mode 1: 16-bit Timer/Counter. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL1).(1) 1 1 Mode 3: Timer 1 halted. Retains count.
7
GATE1
6
C/T1#
5
M11
4
M01
3
GATE0
Timer 0 Gating Control Bit Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0 pin is high and TR0 bit is set. Timer 0 Counter/Timer Select Bit Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. Timer 0 Mode Select Bit M10 M00 Operating mode 0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). 0 1 Mode 1: 16-bit Timer/Counter. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0).(2) 1 1 Mode 3: TL0 is an 8-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1's TR0 and TF0 bits.
2
C/T0#
1
M10
0
M00
Notes:
1. Reloaded from TH1 at overflow. 2. Reloaded from TH0 at overflow.
Reset Value = 0000 0000b Table 62. TH0 Register TH0 (S:8Ch) - Timer 0 High Byte Register
7 Bit Number 7:0 6 5 4 3 2 1 0 -
Bit Mnemonic Description High Byte of Timer 0
Reset Value = 0000 0000b
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Table 63. TL0 Register TL0 (S:8Ah) - Timer 0 Low Byte Register
7 Bit Number 7:0 6 5 4 3 2 1 0 -
Bit Mnemonic Description Low Byte of Timer 0
Reset Value = 0000 0000b Table 64. TH1 Register TH1 (S:8Dh) - Timer 1 High Byte Register
7 Bit Number 7:0 6 5 4 3 2 1 0 -
Bit Mnemonic Description High Byte of Timer 1
Reset Value = 0000 0000b Table 65. TL1 Register TL1 (S:8Bh) - Timer 1 Low Byte Register
7 Bit Number 7:0 6 5 4 3 2 1 0 -
Bit Mnemonic Description Low Byte of Timer 1
Reset Value = 0000 0000b
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Watchdog Timer
The AT8xC51SND1C implement a hardware Watchdog Timer (WDT) that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As shown in Figure 38, the 14-bit prescaler is fed by the WDT clock detailed in Section "Watchdog Clock Controller", page 59. The Watchdog Timer Reset register (WDTRST, see Table 67) provides control access to the WDT, while the Watchdog Timer Program register (WDTPRG, see Figure 41) provides time-out period programming. Three operations control the WDT: * * * Chip reset clears and disables the WDT. Programming the time-out value to the WDTPRG register. Writing a specific 2-Byte sequence to the WDTRST register clears and enables the WDT.
Description
Figure 38. WDT Block Diagram
WDT CLOCK /6
14-bit Prescaler
RST
7-bit Counter
OV RST SET
To internal reset
WTO2:0 1Eh-E1h Decoder System Reset
RST EN WDTPRG.2:0 MATCH
OSC CLOCK
Pulse Generator
RST
WDTRST
Watchdog Clock Controller
As shown in Figure 39 the WDT clock (FWDT) is derived from either the peripheral clock (FPER) or the oscillator clock (FOSC) depending on the WTX2 bit in CKCON register. These clocks are issued from the Clock Controller block as detailed in Section "Clock Controller", page 12. When WTX2 bit is set, the WDT clock frequency is fixed and equal to the oscillator clock frequency divided by 2. When cleared, the WDT clock frequency is equal to the oscillator clock frequency divided by 2 in standard mode or to the oscillator clock frequency in X2 mode.
Figure 39. WDT Clock Controller and Symbol
PER CLOCK OSC CLOCK 0 WDT CLOCK
WDT Clock
1
/2 WTX2
CKCON.6
WDT Clock Symbol
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Watchdog Operation
After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and E1h into the WDTRST register. As soon as it is enabled, there is no way except the chip reset to disable it. If it is not cleared using the previous sequence, the WDT overflows and forces a chip reset. This overflow generates a high level 96 oscillator periods pulse on the RST pin to globally reset the application (refer to Section "Power Management", page 46). The WDT time-out period can be adjusted using WTO2:0 bits located in the WDTPRG register accordingly to the formula shown in Figure 40. In this formula, WTOval represents the decimal value of WTO2:0 bits. Table 66 reports the time-out period depending on the WDT frequency. Figure 40. WDT Time-Out Formula
WDTTO= 6 ((214 2WTOval) - 1) FWDT
Table 66. WDT Time-Out Computation
FWDT (ms) WTO2 0 0 0 0 1 1 1 1 WTO1 0 0 1 1 0 0 1 1 WTO0 0 1 0 1 0 1 0 1 6 MHz(1) 16.38 32.77 65.54 131.07 262.14 524.29 1049 2097 8 MHz(1) 12.28 24.57 49.14 98.28 196.56 393.1 786.24 1572 10 MHz(1) 9.83 19.66 39.32 78.64 157.29 314.57 629.15 1258 12 MHz(2) 8.19 16.38 32.77 65.54 131.07 262.14 524.29 1049 16 MHz(2) 6.14 12.28 24.57 49.14 98.28 196.56 393.12 786.24 20 MHz(2) 4.92 9.83 19.66 39.32 78.64 157.29 314.57 629.15
Notes:
1. These frequencies are achieved in X1 mode or in X2 mode when WTX2 = 1: FWDT = FOSC / 2. 2. These frequencies are achieved in X2 mode when WTX2 = 0: FWDT = FOSC.
WDT Behavior during Idle and Power-down Modes
Operation of the WDT during power reduction modes deserves special attention. The WDT continues to count while the AT8xC51SND1C is in Idle mode. This means that you must dedicate some internal or external hardware to service the WDT during Idle mode. One approach is to use a peripheral Timer to generate an interrupt request when the Timer overflows. The interrupt service routine then clears the WDT, reloads the peripheral Timer for the next service period and puts the AT8xC51SND1C back into Idle mode. The Power-down mode stops all phase clocks. This causes the WDT to stop counting and to hold its count. The WDT resumes counting from where it left off if the Powerdown mode is terminated by INT0, INT1 or keyboard interrupt. To ensure that the WDT does not overflow shortly after exiting the Power-down mode, it is recommended to clear the WDT just before entering Power-down mode. The WDT is cleared and disabled if the Power-down mode is terminated by a reset.
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Registers
Table 67. WDTRST Register WDTRST (S:A6h Write only) - Watchdog Timer Reset Register
7 Bit Number 7-0 6 5 4 3 2 1 0 -
Bit Mnemonic Description Watchdog Control Value
Reset Value = XXXX XXXXb Figure 41. WDTPRG Register WDTPRG (S:A7h) - Watchdog Timer Program Register
7 Bit Number 7-3 6 5 4 3 2 WTO2 1 WTO1 0 WTO0
Bit Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set these bits. Watchdog Timer Time-Out Selection Bits Refer to Table 66 for time-out periods.
2-0
WTO2:0
Reset Value = XXXX X000b
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MP3 Decoder
The AT8xC51SND1C implement a MPEG I/II audio layer 3 decoder better known as MP3 decoder. In MPEG I (ISO 11172-3) three layers of compression have been standardized supporting three sampling frequencies: 48, 44.1, and 32 kHz. Among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining CD audio quality. For example, 3 minutes of CD audio (16-bit PCM, 44.1 kHz) data, which needs about 32M bytes of storage, can be encoded into only 2.7M bytes of MPEG I audio layer 3 data. In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16 kHz are supported for low bit rates applications. The AT8xC51SND1C can decode in real-time the MPEG I audio layer 3 encoded data into a PCM audio data, and also supports MPEG II audio layer 3 additional frequencies. Additional features are supported by the AT8xC51SND1C MP3 decoder such as volume control, bass, medium, and treble controls, bass boost effect and ancillary data extraction.
Decoder
Description The C51 core interfaces to the MP3 decoder through nine special function registers: MP3CON, the MP3 Control register (see Table 72); MP3STA, the MP3 Status register (see Table 73); MP3DAT, the MP3 Data register (see Table 74); MP3ANC, the Ancillary Data register (see Table 76); MP3VOL and MP3VOR, the MP3 Volume Left and Right Control registers (see Table 77 and Table 78); MP3BAS, MP3MED, and MP3TRE, the MP3 Bass, Medium, and Treble Control registers (see Table 79, Table 80, and Table 81); and MPCLK, the MP3 Clock Divider register (see Table 82). Figure 42 shows the MP3 decoder block diagram.
Figure 42. MP3 Decoder Block Diagram
Audio Data From C51
8
1K Bytes Frame Buffer MP3DAT
Header Checker Huffman Decoder
Dequantizer
Stereo Processor
Side Information
MPxREQ
MP3 CLOCK
MP3STA1.n
ERRxxx MPFS1:0 MPVER
MP3STA.5:3 MP3STA.2:1 MP3STA.0
Ancillary Buffer MP3ANC
MPEN
MP3CON.7
Anti-Aliasing
IMDCT
Sub-band Synthesis
16
Decoded Data To Audio Interface
MPBBST
MP3CON.6
MP3VOL
MP3VOR
MP3BAS
MP3MED
MP3TRE
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MP3 Data The MP3 decoder does not start any frame decoding before having a complete frame in its input buffer(1). In order to manage the load of MP3 data in the frame buffer, a hardware handshake consisting of data request and data acknowledgment is implemented. Each time the MP3 decoder needs MP3 data, it sets the MPREQ, MPFREQ and MPBREQ flags respectively in MP3STA and MP3STA1 registers. MPREQ flag can generate an interrupt if enabled as explained in Section "Interrupt". The CPU must then load data in the buffer by writing it through MP3DAT register thus acknowledging the previous request. As shown in Figure 43, the MPFREQ flag remains set while data (i.e a frame) is requested by the decoder. It is cleared when no more data is requested and set again when new data are requested. MPBREQ flag toggles at every Byte writing.
Note: 1. The first request after enable, consists in 1024 Bytes of data to fill in the input buffer.
Figure 43. Data Timing Diagram
MPREQ Flag MPFREQ Flag MPBREQ Flag Write to MP3DAT
Cleared when Reading MP3STA
MP3 Clock
The MP3 decoder clock is generated by division of the PLL clock. The division factor is given by MPCD4:0 bits in MP3CLK register. Figure 44 shows the MP3 decoder clock generator and its calculation formula. The MP3 decoder clock frequency depends only on the incoming MP3 frames. Figure 44. MP3 Clock Generator and Symbol
MP3CLK PLL CLOCK MPCD4:0 MP3 Decoder Clock MP3 CLOCK MP3 Clock Symbol
PLLclk MP3clk = ---------------------------MPCD + 1
As soon as the frame header has been decoded and the MPEG version extracted, the minimum MP3 input frequency must be programmed according to Table 68. Table 68. MP3 Clock Frequency
MPEG Version I II Minimum MP3 Clock (MHz) 21 10.5
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Audio Controls
Volume Control The MP3 decoder implements volume control on both right and left channels. The MP3VOR and MP3VOL registers allow a 32-step volume control according to Table 69. Table 69. Volume Control
VOL4:0 or VOR4:0 00000 00001 00010 11110 11111 Volume Gain (dB) Mute -33 -27 -1.5 0
Equalization Control
Sound can be adjusted using a 3-band equalizer: a bass band under 750 Hz, a medium band from 750 Hz to 3300 Hz and a treble band over 3300 Hz. The MP3BAS, MP3MED, and MP3TRE registers allow a 32-step gain control in each band according to Table 70. Table 70. Bass, Medium, Treble Control
BAS4:0 or MED4:0 or TRE4:0 00000 00001 00010 11110 11111 Gain (dB) - -14 -10 +1 +1.5
Special Effect
The MPBBST bit in MP3CON register allows enabling of a bass boost effect with the following characteristics: gain increase of +9 dB in the frequency under 375 Hz. The three different errors that can appear during frame processing are detailed in the following sections. All these errors can trigger an interrupt as explained in Section "Interrupt", page 66. The ERRSYN flag in MP3STA is set when a non-supported layer is decoded in the header of the frame that has been sent to the decoder. The ERRSYN flag in MP3STA is set when no synchronization pattern is found in the data that have been sent to the decoder. When the CRC of a frame does not match the one calculated, the flag ERRCRC in MP3STA is set. In this case, depending on the CRCEN bit in MP3CON, the frame is played or rejected. In both cases, noise may appear at audio output.
Decoding Errors
Layer Error
Synchronization Error
CRC Error
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Frame Information
The MP3 frame header contains information on the audio data contained in the frame. These informations is made available in the MP3STA register for you information. MPVER and MPFS1:0 bits allow decoding of the sampling frequency according to Table 71. MPVER bit gives the MPEG version (2 or 1). Table 71. MP3 Frame Frequency Sampling
MPVER 0 0 0 0 1 1 1 1 MPFS1 0 0 1 1 0 0 1 1 MPFS0 0 1 0 1 0 1 0 1 Fs (kHz) 22.05 (MPEG II) 24 (MPEG II) 16 (MPEG II) Reserved 44.1 (MPEG I) 48 (MPEG I) 32 (MPEG I) Reserved
Ancillary Data
MP3 frames also contain data bits called ancillary data. These data are made available in the MP3ANC register for each frame. As shown in Figure 45, the ancillary data are available by Bytes when MPANC flag in MP3STA register is set. MPANC flag is set when the ancillary buffer is not empty (at least one ancillary data is available) and is cleared only when there is no more ancillary data in the buffer. This flag can generate an interrupt as explained in Section "Interrupt", page 66. When set, software must read all Bytes to empty the ancillary buffer. Figure 45. Ancillary Data Block Diagram
Ancillary Data To C51
8
MP3ANC
8
7-Byte Ancillary Buffer
MPANC
MP3STA.7
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Interrupt
Description As shown in Figure 46, the MP3 decoder implements five interrupt sources reported in ERRCRC, ERRSYN, ERRLAY, MPREQ, and MPANC flags in MP3STA register. All these sources are maskable separately using MSKCRC, MSKSYN, MSKLAY, MSKREQ, and MSKANC mask bits respectively in MP3CON register. The MP3 interrupt is enabled by setting EMP3 bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register. All interrupt flags but MPREQ and MPANC are cleared when reading MP3STA register. The MPREQ flag is cleared by hardware when no more data is requested (see Figure 43) and MPANC flag is cleared by hardware when the ancillary buffer becomes empty. Figure 46. MP3 Decoder Interrupt System
MPANC
MP3STA.7
MSKANC MPREQ
MP3STA.6 MP3CON.4
MSKREQ ERRLAY
MP3STA.5 MP3CON.3
MP3 Decoder Interrupt Request MSKLAY EMP3
IEN0.5
ERRSYN
MP3STA.4
MP3CON.2
MSKSYN ERRCRC
MP3STA.3 MP3CON.1
MSKCRC
MP3CON.0
Management
Reading the MP3STA register automatically clears the interrupt flags (acknowledgment) except the MPREQ and MPANC flags. This implies that register content must be saved and tested, interrupt flag by interrupt flag to be sure not to forget any interrupts.
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Figure 47. MP3 Interrupt Service Routine Flow
MP3 Decoder ISR
Read MP3STA
Data Request? MPFREQ = 1?
Data Request Handler
Ancillary Data?(1) MPANC = 1?
Write MP3 Data to MP3DAT
Ancillary Data Handler
Sync Error?(1) ERRSYN = 1?
Read ANN2:0 Ancillary Bytes From MP3ANC
Synchro Error Handler
Layer Error?(1) ERRSYN = 1?
Reload MP3 Frame Through MP3DAT
Layer Error Handler CRC Error Handler
Load New MP3 Frame Through MP3DAT
Note:
1. Test these bits only if needed (unmasked interrupt).
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Registers
Table 72. MP3CON Register MP3CON (S:AAh) - MP3 Decoder Control Register
7 MPEN Bit Number 6 MPBBST 5 CRCEN 4 MSKANC 3 MSKREQ 2 MSKLAY 1 MSKSYN 0 MSKCRC
Bit Mnemonic Description MP3 Decoder Enable Bit Set to enable the MP3 decoder. Clear to disable the MP3 decoder. Bass Boost Bit Set to enable the bass boost sound effect. Clear to disable the bass boost sound effect. CRC Check Enable Bit Set to enable processing of frame that contains CRC error. Frame is played whatever the error. Clear to disable processing of frame that contains CRC error. Frame is skipped. MPANC Flag Mask Bit Set to prevent the MPANC flag from generating a MP3 interrupt. Clear to allow the MPANC flag to generate a MP3 interrupt. MPREQ Flag Mask Bit Set to prevent the MPREQ flag from generating a MP3 interrupt. Clear to allow the MPREQ flag to generate a MP3 interrupt. ERRLAY Flag Mask Bit Set to prevent the ERRLAY flag from generating a MP3 interrupt. Clear to allow the ERRLAY flag to generate a MP3 interrupt. ERRSYN Flag Mask Bit Set to prevent the ERRSYN flag from generating a MP3 interrupt. Clear to allow the ERRSYN flag to generate a MP3 interrupt. ERRCRC Flag Mask Bit Set to prevent the ERRCRC flag from generating a MP3 interrupt. Clear to allow the ERRCRC flag to generate a MP3 interrupt.
7
MPEN
6
MPBBST
5
CRCEN
4
MSKANC
3
MSKREQ
2
MSKLAY
1
MSKSYN
0
MSKCRC
Reset Value = 0011 1111b
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Table 73. MP3STA Register MP3STA (S:C8h Read Only) - MP3 Decoder Status Register
7 MPANC Bit Number 6 MPREQ 5 ERRLAY 4 ERRSYN 3 ERRCRC 2 MPFS1 1 MPFS0 0 MPVER
Bit Mnemonic Description Ancillary Data Available Flag Set by hardware as soon as one ancillary data is available (buffer not empty). Cleared by hardware when no more ancillary data is available (buffer empty). MP3 Data Request Flag Set by hardware when MP3 decoder request data. Cleared when reading MP3STA. Invalid Layer Error Flag Set by hardware when an invalid layer is encountered. Cleared when reading MP3STA. Frame Synchronization Error Flag Set by hardware when no synchronization pattern is encountered in a frame. Cleared when reading MP3STA. CRC Error Flag Set by hardware when a frame handling CRC is corrupted. Cleared when reading MP3STA. Frequency Sampling Bits Refer to Table 71 for bits description. MPEG Version Bit Set by the MP3 decoder when the loaded frame is a MPEG I frame. Cleared by the MP3 decoder when the loaded frame is a MPEG II frame.
7
MPANC
6
MPREQ
5
ERRLAY
4
ERRSYN
3
ERRCRC
2-1
MPFS1:0
0
MPVER
Reset Value = 0000 0001b Table 74. MP3DAT Register MP3DAT (S:ACh) - MP3 Data Register
7 MPD7 Bit Number 7-0 6 MPD6 5 MPD5 4 MPD4 3 MPD3 2 MPD2 1 MPD1 0 MPD0
Bit Mnemonic Description MPD7:0 Input Stream Data Buffer 8-bit MP3 stream data input buffer.
Reset Value = 0000 0000b
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Table 75. MP3STA1 Register MP3STA1 (S:AFh) - MP3 Decoder Status Register 1
7 Bit Number 7-5 6 5 4 MPFREQ 3 MPFREQ 2 1 0 -
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. MP3 Frame Data Request Flag Set by hardware when MP3 decoder request data. Cleared when MP3 decoder no more request data . MP3 Byte Data Request Flag Set by hardware when MP3 decoder request data. Cleared when writing to MP3DAT. Reserved The value read from these bits is always 0. Do not set these bits.
4
MPFREQ
3
MPBREQ
2-0
-
Reset Value = 0001 0001b Table 76. MP3ANC Register MP3ANC (S:ADh Read Only) - MP3 Ancillary Data Register
7 AND7 Bit Number 7-0 6 AND6 5 AND5 4 AND4 3 AND3 2 AND2 1 AND1 0 AND0
Bit Mnemonic Description AND7:0 Ancillary Data Buffer MP3 ancillary data Byte buffer.
Reset Value = 0000 0000b Table 77. MP3VOL Register MP3VOL (S:9Eh) - MP3 Volume Left Control Register
7 Bit Number 7-5 6 5 4 VOL4 3 VOL3 2 VOL2 1 VOL1 0 VOL0
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Volume Left Value Refer to Table 69 for the left channel volume control description.
4-0
VOL4:0
Reset Value = 0000 0000b
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Table 78. MP3VOR Register MP3VOR (S:9Fh) - MP3 Volume Right Control Register
7 Bit Number 7-5 6 5 4 VOR4 3 VOR3 2 VOR2 1 VOR1 0 VOR0
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Volume Right Value Refer to Table 69 for the right channel volume control description.
4-0
VOR4:0
Reset Value = 0000 0000b Table 79. MP3BAS Register MP3BAS (S:B4h) - MP3 Bass Control Register
7 Bit Number 7-5 6 5 4 BAS4 3 BAS3 2 BAS2 1 BAS1 0 BAS0
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Bass Gain Value Refer to Table 70 for the bass control description.
4-0
BAS4:0
Reset Value = 0000 0000b Table 80. MP3MED Register MP3MED (S:B5h) - MP3 Medium Control Register
7 Bit Number 7-6 6 5 MED5 4 MED4 3 MED3 2 MED2 1 MED1 0 MED0
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Medium Gain Value Refer to Table 70 for the medium control description.
5-0
MED5:0
Reset Value = 0000 0000b
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Table 81. MP3TRE Register MP3TRE (S:B6h) - MP3 Treble Control Register
7 Bit Number 7-6 6 5 TRE5 4 TRE4 3 TRE3 2 TRE2 1 TRE1 0 TRE0
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Treble Gain Value Refer to Table 70 for the treble control description.
5-0
TRE5:0
Reset Value = 0000 0000b Table 82. MP3CLK Register MP3CLK (S:EBh) - MP3 Clock Divider Register
7 Bit Number 7-5 6 5 4 MPCD4 3 MPCD3 2 MPCD2 1 MPCD1 0 MPCD0
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. MP3 Decoder Clock Divider 5-bit divider for MP3 decoder clock generation.
4-0
MPCD4:0
Reset Value = 0000 0000b
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Audio Output Interface
The AT8xC51SND1C implement an audio output interface allowing the audio bitstream to be output in various formats. It is compatible with right and left justification PCM and I2S formats and thanks to the on-chip PLL (see Section "Clock Controller", page 12) allows connection of almost all of the commercial audio DAC families available on the market. The audio bitstream can be from 2 different types: * * The MP3 decoded bitstream coming from the MP3 decoder for playing songs. The audio bitstream coming from the MCU for outputting voice or sounds.
Description
The C51 core interfaces to the audio interface through five special function registers: AUDCON0 and AUDCON1, the Audio Control registers (see Table 84 and Table 85); AUDSTA, the Audio Status register (see Table 86); AUDDAT, the Audio Data register (see Table 87); and AUDCLK, the Audio Clock Divider register (see Table 88). Figure 48 shows the audio interface block diagram, blocks are detailed in the following sections.
Figure 48. Audio Interface Block Diagram
SCLK
AUD CLOCK
DCLK Clock Generator
0
AUDEN
AUDCON1.0
DSEL
1
HLR Data Ready Audio Data From MP3 Decoder Sample Request To MP3 Decoder
AUDCON0.0
DSIZ
AUDCON0.1
POL
AUDCON0.2
16
MP3 Buffer
16 16
0 1
Data Converter
DOUT
DRQEN
AUDCON1.6
JUST4:0 SRC
AUDCON1.7 AUDCON0.7:3
SREQ Audio Data From C51
8
Audio Buffer AUDDAT
AUDSTA.7
UDRN
AUDSTA.6
AUBUSY DUP1:0
AUDCON1.2:1 AUDSTA.5
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Clock Generator
The audio interface clock is generated by division of the PLL clock. The division factor is given by AUCD4:0 bits in CLKAUD register. Figure 49 shows the audio interface clock generator and its calculation formula. The audio interface clock frequency depends on the incoming MP3 frames and the audio DAC used. Figure 49. Audio Clock Generator and Symbol
AUDCLK
PLL CLOCK
AUCD4:0
Audio Interface Clock
AUD CLOCK
PLLclk AUDclk = --------------------------AUCD + 1
Audio Clock Symbol
As soon as audio interface is enabled by setting AUDEN bit in AUDCON1 register, the master clock generated by the PLL is output on the SCLK pin which is the DAC system clock. This clock is output at 256 or 384 times the sampling frequency depending on the DAC capabilities. HLR bit in AUDCON0 register must be set according to this rate for properly generating the audio bit clock on the DCLK pin and the word selection clock on the DSEL pin. These clocks are not generated when no data is available at the data converter input. For DAC compatibility, the bit clock frequency is programmable for outputting 16 bits or 32 bits per channel using the DSIZ bit in AUDCON0 register (see Section "Data Converter", page 74), and the word selection signal is programmable for outputting left channel on low or high level according to POL bit in AUDCON0 register as shown in Figure 50. Figure 50. DSEL Output Polarity
POL = 0 POL = 1
Left Channel Left Channel Right Channel Right Channel
Data Converter
The data converter block converts the audio stream input from the 16-bit parallel format to a serial format. For accepting all PCM formats and I 2 S format, JUST4:0 bits in AUDCON0 register are used to shift the data output point. As shown in Figure 51, these bits allow MSB justification by setting JUST4:0 = 00000, LSB justification by setting JUST4:0 = 10000, I2S Justification by setting JUST4:0 = 00001, and more than 16-bit LSB justification by filling the low significant bits with logic 0.
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Figure 51. Audio Output Format
DSEL DCLK DOUT
1 2 3
Left Channel
13 14 15 16 1 2 3
Right Channel
13 14 15 16
LSB MSB B14
B1
LSB MSB B14
B1
I2S Format with DSIZ = 0 and JUST4:0 = 00001.
DSEL DCLK DOUT
1 2 3
Left Channel
17 18 32 1 2 3
Right Channel
17 18 32
MSB B14
LSB
MSB B14
LSB
I2S Format with DSIZ = 1 and JUST4:0 = 00001.
DSEL DCLK DOUT
1 2 3
Left Channel
13 14 15 16 1 2 3
Right Channel
13 14 15 16
MSB B14
B1
LSB MSB B15
B1
LSB
MSB/LSB Justified Format with DSIZ = 0 and JUST4:0 = 00000.
DSEL DCLK DOUT
1
Left Channel
16 17 18 31 32 1
Right Channel
16 17 18 31 32
MSB B14
B1
LSB
MSB B14
B1
LSB
16-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 10000.
DSEL DCLK DOUT
1
Left Channel
15 16 30 31 32 1
Right Channel
15 16 30 31 32
MSB B16
B2
B1
LSB
MSB B16
B2
B1
LSB
18-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 01110.
The data converter receives its audio stream from 2 sources selected by the SRC bit in AUDCON1 register. When cleared, the audio stream comes from the MP3 decoder (see Section "MP3 Decoder", page 62) for song playing. When set, the audio stream is coming from the C51 core for voice or sound playing. As soon as first audio data is input to the data converter, it enables the clock generator for generating the bit and word clocks.
Audio Buffer
In voice or sound playing mode, the audio stream comes from the C51 core through an audio buffer. The data is in 8-bit format and is sampled at 8 kHz. The audio buffer adapts the sample format and rate. The sample format is extended to 16 bits by filling the LSB to 00h. Rate is adapted to the DAC rate by duplicating the data using DUP1:0 bits in AUDCON1 register according to Table 83. The audio buffer interfaces to the C51 core through three flags: the sample request flag (SREQ in AUDSTA register), the under-run flag (UNDR in AUDSTA register) and the busy flag (AUBUSY in AUDSTA register). SREQ and UNDR can generate an interrupt request as explained in Section "Interrupt Request", page 76. The buffer size is 8 Bytes large. SREQ is set when the samples number switches from 4 to 3 and reset when the samples number switches from 4 to 5; UNDR is set when the buffer becomes empty signaling that the audio interface ran out of samples; and AUBUSY is set when the buffer is full.
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Table 83. Sample Duplication Factor
DUP1 0 0 1 1 DUP0 0 1 0 1 Factor No sample duplication, DAC rate = 8 kHz (C51 rate). One sample duplication, DAC rate = 16 kHz (2 x C51 rate). 2 samples duplication, DAC rate = 32 kHz (4 x C51 rate). Three samples duplication, DAC rate = 48 kHz (6 x C51 rate).
MP3 Buffer
In song playing mode, the audio stream comes from the MP3 decoder through a buffer. The MP3 buffer is used to store the decoded MP3 data and interfaces to the decoder through a 16-bit data input and data request signal. This signal asks for data when the buffer has enough space to receive new data. Data request is conditioned by the DREQEN bit in AUDCON1 register. When set, the buffer requests data to the MP3 decoder. When cleared no more data is requested but data are output until the buffer is empty. This bit can be used to suspend the audio generation (pause mode). The audio interrupt request can be generated by 2 sources when in C51 audio mode: a sample request when SREQ flag in AUDSTA register is set to logic 1, and an under-run condition when UDRN flag in AUDSTA register is set to logic 1. Both sources can be enabled separately by masking one of them using the MSREQ and MUDRN bits in AUDCON1 register. A global enable of the audio interface is provided by setting the EAUD bit in IEN0 register. The interrupt is requested each time one of the 2 sources is set to one. The source flags are cleared by writing some data in the audio buffer through AUDDAT, but the global audio interrupt flag is cleared by hardware when the interrupt service routine is executed. Figure 52. Audio Interface Interrupt System
UDRN
AUDSTA.6
Interrupt Request
MUDRN
AUDCON1.4
Audio Interrupt Request EAUD
IEN0.6
SREQ
AUDSTA.7
MSREQ
AUDCON1.5
MP3 Song Playing
In MP3 song playing mode, the operations to do are to configure the PLL and the audio interface according to the DAC selected. The audio clock is programmed to generate the 256*Fs or 384*Fs as explained in Section "Clock Generator", page 74. Figure 53 shows the configuration flow of the audio interface when in MP3 song mode.
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Figure 53. MP3 Mode Audio Configuration Flow
MP3 Mode Configuration
Enable DAC System Clock AUDEN = 1
Program Audio Clock
Configure Interface HLR = X DSIZ = X POL = X JUST4:0 = XXXXXb SRC = 0
Wait For DAC Set-up Time
Enable Data Request DRQEN = 1
Voice or Sound Playing
In voice or sound playing mode, the operations required are to configure the PLL and the audio interface according to the DAC selected. The audio clock is programmed to generate the 256*Fs or 384*Fs as for the MP3 playing mode. The data flow sent by the C51 is then regulated by interrupt and data is loaded 4 Bytes by 4 Bytes. Figure 54 shows the configuration flow of the audio interface when in voice or sound mode.
Figure 54. Voice or Sound Mode Audio Flows
Voice/Song Mode Configuration Audio Interrupt Service Routine
Program Audio Clock
Wait for DAC Enable Time
Sample Request? SREQ = 1?
Configure Interface HLR = X DSIZ = X POL = X JUST4:0 = XXXXXb DUP1:0 = XX
Select Audio SRC = 1 Load 4 Samples in the Audio Buffer Load 8 Samples in the Audio Buffer Under-run Condition1
Enable DAC System Clock AUDEN = 1
Enable Interrupt Set MSREQ & MUDRN1 EAUD = 1
Note:
1. An under-run occurrence signifies that C51 core did not respond to the previous sample request interrupt. It may never occur for a correct voice/sound generation. It is the user's responsibility to mask it or not.
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Registers
Table 84. AUDCON0 Register AUDCON0 (S:9Ah) - Audio Interface Control Register 0
7 JUST4 Bit Number 7-3 6 JUST3 5 JUST2 4 JUST1 3 JUST0 2 POL 1 DSIZ 0 HLR
Bit Mnemonic Description JUST4:0 Audio Stream Justification Bits Refer to Section "Data Converter", page 74 for bits description. DSEL Signal Output Polarity Set to output the left channel on high level of DSEL output (PCM mode). Clear to output the left channel on the low level of DSEL output (I2S mode). Audio Data Size Set to select 32-bit data output format. Clear to select 16-bit data output format. High/Low Rate Bit Set by software when the PLL clock frequency is 384*Fs. Clear by software when the PLL clock frequency is 256*Fs.
2
POL
1
DSIZ
0
HLR
Reset Value = 0000 1000b Table 85. AUDCON1 Register AUDCON1 (S:9Bh) - Audio Interface Control Register 1
7 SRC Bit Number 6 DRQEN 5 MSREQ 4 MUDRN 3 2 DUP1 1 DUP0 0 AUDEN
Bit Mnemonic Description Audio Source Bit Set to select C51 as audio source for voice or sound playing. Clear to select the MP3 decoder output as audio source for song playing. MP3 Decoded Data Request Enable Bit Set to enable data request to the MP3 decoder and to start playing song. Clear to disable data request to the MP3 decoder. Audio Sample Request Flag Mask Bit Set to prevent the SREQ flag from generating an audio interrupt. Clear to allow the SREQ flag to generate an audio interrupt. Audio Sample Under-run Flag Mask Bit Set to prevent the UDRN flag from generating an audio interrupt. Clear to allow the UDRN flag to generate an audio interrupt. Reserved The value read from this bit is always 0. Do not set this bit. Audio Duplication Factor Refer to Table 83 for bits description. Audio Interface Enable Bit Set to enable the audio interface. Clear to disable the audio interface.
7
SRC
6
DRQEN
5
MSREQ
4
MUDRN
3
-
2-1
DUP1:0
0
AUDEN
Reset Value = 1011 0010b
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Table 86. AUDSTA Register AUDSTA (S:9Ch Read Only) - Audio Interface Status Register
7 SREQ Bit Number 6 UDRN 5 AUBUSY 4 3 2 1 0 -
Bit Mnemonic Description Audio Sample Request Flag Set in C51 audio source mode when the audio interface request samples (buffer half empty). This bit generates an interrupt if not masked and if enabled in IEN0. Cleared by hardware when samples are loaded in AUDDAT. Audio Sample Under-run Flag Set in C51 audio source mode when the audio interface runs out of samples (buffer empty). This bit generates an interrupt if not masked and if enabled in IEN0. Cleared by hardware when samples are loaded in AUDDAT. Audio Interface Busy Bit Set in C51 audio source mode when the audio interface can not accept more sample (buffer full). Cleared by hardware when buffer is no more full. Reserved The value read from these bits is always 0. Do not set these bits.
7
SREQ
6
UDRN
5
AUBUSY
4-0
-
Reset Value = 1100 0000b Table 87. AUDDAT Register AUDDAT (S:9Dh) - Audio Interface Data Register
7 AUD7 Bit Number 7-0 6 AUD6 5 AUD5 4 AUD4 3 AUD3 2 AUD2 1 AUD1 0 AUD0
Bit Mnemonic Description AUD7:0 Audio Data 8-bit sampling data for voice or sound playing.
Reset Value = 1111 1111b Table 88. AUDCLK Register AUDCLK (S:ECh) - Audio Clock Divider Register
7 Bit Number 7-5 6 5 4 AUCD4 3 AUCD3 2 AUCD2 1 AUCD1 0 AUCD0
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Audio Clock Divider 5-bit divider for audio clock generation.
4-0
AUCD4:0
Reset Value = 0000 0000b
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Universal Serial Bus
The AT8xC51SND1C implements a USB device controller supporting full speed data transfer. In addition to the default control endpoint 0, it provides 2 other endpoints, which can be configured in control, bulk, interrupt or isochronous modes: * * Endpoint 0: 32-Byte FIFO, default control endpoint Endpoint 1, 2: 64-Byte Ping-pong FIFO,
This allows the firmware to be developed conforming to most USB device classes, for example: * * * USB Mass Storage Class Bulk-Only Transport USB Mass Storage Class Bulk-only Transport, Revision 1.0 - September 31, 1999 USB Human Interface Device Class, Version 1.1 - April 7, 1999 USB Device Firmware Upgrade Class, Revision 1.0 - May 13, 1999
Within the Bulk-only framework, the Control endpoint is only used to transport classspecific and standard USB requests for device set-up and configuration. One Bulk-out endpoint is used to transport commands and data from the host to the device. One Bulk in endpoint is used to transport status and data from the device to the host. The following AT8xC51SND1C configuration adheres to those requirements: * * * Endpoint 0: 32 Bytes, Control In-Out Endpoint 1: 64 Bytes, Bulk-in Endpoint 2: 64 Bytes, Bulk-out
USB Device Firmware Upgrade (DFU)
The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chip Flash memory of the AT89C51SND1C. This allows installing product enhancements and patches to devices that are already in the field. 2 different configurations and descriptor sets are used to support DFU functions. The Run-Time configuration co-exist with the usual functions of the device, which is USB Mass Storage for AT89C51SND1C. It is used to initiate DFU from the normal operating mode. The DFU configuration is used to perform the firmware update after device re-configuration and USB reset. It excludes any other function. Only the default control pipe (endpoint 0) is used to support DFU services in both configurations. The only possible value for the MaxPacketSize in the DFU configuration is 32 Bytes, which is the size of the FIFO implemented for endpoint 0.
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Description
The USB device controller provides the hardware that the AT8xC51SND1C needs to interface a USB link to a data flow stored in a double port memory. It requires a 48 MHz reference clock provided by the clock controller as detailed in Section "Clock Controller", page 81. This clock is used to generate a 12 MHz Full Speed bit clock from the received USB differential data flow and to transmit data according to full speed USB device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block. The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuffing, CRC generation and checking, and the serial-parallel data conversion. The Universal Function Interface (UFI) controls the interface between the data flow and the Dual Port RAM, but also the interface with the C51 core itself. Figure 55. USB Device Controller Block Diagram
USB CLOCK
48 MHz
DPLL
12 MHz
D+ D-
USB Buffer
UFI
To/From C51 Core
SIE
Clock Controller
The USB controller clock is generated by division of the PLL clock. The division factor is given by USBCD1:0 bits in USBCLK register (see Table 104). Figure 56 shows the USB controller clock generator and its calculation formula. The USB controller clock frequency must always be 48 MHz. Figure 56. USB Clock Generator and Symbol
USBCLK PLL CLOCK USBCD1:0 48 MHz USB Clock USB CLOCK USB Clock Symbol
PLLclk USBclk = ------------------------------USBCD + 1
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Serial Interface Engine (SIE)
The SIE performs the following functions: * * * * * * * NRZI data encoding and decoding. Bit stuffing and unstuffing. CRC generation and checking. ACKs and NACKs automatic generation. TOKEN type identifying. Address checking. Clock recovery (using DPLL).
Figure 57. SIE Block Diagram
End of Packet Detector Start of Packet Detector SYNC Detector
NRZI ` NRZ Bit Unstuffing Packet Bit Counter D+ DUSB 48 MHz CLOCK
PID Decoder
Clock Recover
Address Decoder Serial to Parallel Converter
SysClk (12 MHz)
8
Data Out
CRC5 & CRC16 Generator/Check USB Pattern Generator Parallel to Serial Converter Bit Stuffing NRZI Converter CRC16 Generator
8
Data In
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Function Interface Unit (UFI) The Function Interface Unit provides the interface between the AT8xC51SND1C and the SIE. It manages transactions at the packet level with minimal intervention from the device firmware, which reads and writes the endpoint FIFOs. Figure 59 shows typical USB IN and OUT transactions reporting the split in the hardware (UFI) and software (C51) load. Figure 58. UFI Block Diagram
USBCON USBADDR USBINT USBIEN UEPNUM UEPCONX UEPSTAX UEPRST UEPINT UEPIEN UEPDATX UBYCTX UFNUMH UFNUML
12 MHz DPLL
Transfer Control FSM
Asynchronous Information
To/From C51 Core
To/From SIE
Endpoint Control USB side
Endpoint 2 Endpoint 1 Endpoint 0
Endpoint Control C51 side
Figure 59. USB Typical Transaction Load OUT Transactions:
HOST
OUT DATA0 (n Bytes) ACK OUT C51 interrupt DATA1 NACK OUT DATA1 ACK
UFI C51 IN Transactions:
HOST UFI C51
IN NACK
Endpoint FIFO read (n Bytes)
IN DATA1
IN DATA1
ACK C51 interrupt Endpoint FIFO write
Endpoint FIFO Write
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Configuration
General Configuration * USB controller enable Before any USB transaction, the 48 MHz required by the USB controller must be correctly generated (See "Clock Controller" on page 19). The USB controller should be then enabled by setting the EUSB bit in the USBCON register. * Set address After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the USBADDR register. This action will allow the USB controller to answer to the requests sent at the address 0. When a SET_ADDRESS request has been received, the USB controller must only answer to the address defined by the request. The new address should be stored in the USBADDR register. The FEN bit and the FADDEN bit in the USBCON register should be set to allow the USB controller to answer only to requests sent at the new address. * Set configuration The CONFG bit in the USBCON register should be set after a SET_CONFIGURATION request with a non-zero value. Otherwise, this bit should be cleared. Endpoint Configuration * Selection of an Endpoint The endpoint register access is performed using the UEPNUM register. The registers - - - - UEPSTAX UEPCONX UEPDATX UBYCTX
Theses registers correspond to the endpoint whose number is stored in the UEPNUM register. To select an Endpoint, the firmware has to write the endpoint number in the UEPNUM register. Figure 60. Endpoint Selection
UEPSTA0 UEPCON0 UBYCT0 UEPDAT0
Endpoint 0
0 1 X
UEPSTAX
SFR Registers
UEPCONX UBYCTX UEPDATX
Endpoint 2
UEPSTA2
UEPCON2 UBYCT2
UEPDAT2
2
UEPNUM
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* Endpoint enable Before using an endpoint, this must be enabled by setting the EPEN bit in the UEPCONX register. An endpoint which is not enabled won't answer to any USB request. The Default Control Endpoint (Endpoint 0) should always be enabled in order to answer to USB standard requests. * Endpoint type configuration All Standard Endpoints can be configured in Control, Bulk, Interrupt or Isochronous mode. The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous mode. The configuration of an endpoint is performed by setting the field EPTYPE with the following values: - - - - Control: Bulk: Interrupt: EPTYPE = 00b EPTYPE = 10b EPTYPE = 11b Isochronous: EPTYPE = 01b
The Endpoint 0 is the Default Control Endpoint and should always be configured in Control type. * Endpoint direction configuration For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the EPDIR bit of the UEPCONX register with the following values: - - * IN: OUT: EPDIR = 1b EPDIR = 0b
For Control endpoints, the EPDIR bit has no effect. Summary of Endpoint Configuration: Do not forget to select the correct endpoint number in the UEPNUM register before accessing endpoint specific registers. Table 89. Summary of Endpoint Configuration
Endpoint Configuration Disabled Control Bulk-in Bulk-out Interrupt-In Interrupt-Out Isochronous-In Isochronous-Out EPEN 0b 1b 1b 1b 1b 1b 1b 1b EPDIR Xb Xb 1b 0b 1b 0b 1b 0b EPTYPE XXb 00b 10b 10b 11b 11b 01b 01b UEPCONX 0XXX XXXb 80h 86h 82h 87h 83h 85h 81h
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*
Endpoint FIFO reset Before using an endpoint, its FIFO should be reset. This action resets the FIFO pointer to its original value, resets the Byte counter of the endpoint (UBYCTX register), and resets the data toggle bit (DTGL bit in UEPCONX). The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the corresponding bit in the UEPRST register. For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then 0000 0000b in the UEPRST register. Note that the endpoint reset doesn't reset the bank number for ping-pong endpoints.
Read/Write Data FIFO
Read Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register. After a new valid packet has been received on an Endpoint, the data are stored into the FIFO and the Byte counter of the endpoint is updated (UBYCTX registers). The firmware has to store the endpoint Byte counter before any access to the endpoint FIFO. The Byte counter is not updated when reading the FIFO. To read data from an endpoint, select the correct endpoint number in UEPNUM and read the UEPDATX register. This action automatically decreases the corresponding address vector, and the next data is then available in the UEPDATX register. Write Data FIFO The write access for each IN endpoint is performed using the UEPDATX register. To write a Byte into an IN endpoint FIFO, select the correct endpoint number in UEPNUM and write into the UEPDATX register. The corresponding address vector is automatically increased, and another write can be carried out. Warning 1: The Byte counter is not updated. Warning 2: Do not write more Bytes than supported by the corresponding endpoint. FIFO Mapping Figure 61. Endpoint FIFO Configuration
Endpoint 0
UEPSTA0
UEPCON0 UBYCT0
UEPDAT0
0 1 X
UEPSTAX
SFR Registers
UEPCONX UBYCTX UEPDATX
Endpoint 2
UEPSTA2
UEPCON2 UBYCT2
UEPDAT2
2
UEPNUM
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Bulk/Interrupt Transactions
Bulk/Interrupt OUT Transactions in Standard Mode Bulk and Interrupt transactions are managed in the same way.
Figure 62. Bulk/Interrupt OUT transactions in Standard Mode
HOST
OUT DATA0 (n Bytes)
UFI
ACK RXOUTB0
C51
Endpoint FIFO Read Byte 1 OUT DATA1 NAK OUT DATA1 NAK OUT DATA1 ACK RXOUTB0 Endpoint FIFO Read Byte 1 Endpoint FIFO Read Byte n Clear RXOUTB0 Endpoint FIFO Read Byte 2
An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt packets. When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data Bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUTB0 bit to allow the USB controller to accept the next OUT packet on this endpoint. Until the RXOUTB0 bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each OUT requests. If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won't be stored, but the USB controller will consider that the packet is valid if the CRC is correct and the endpoint Byte counter contains the number of Bytes sent by the Host.
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Bulk/Interrupt OUT Transactions in Ping-pong Mode
Figure 63. Bulk/Interrupt OUT Transactions in Ping-pong Mode
HOST
OUT DATA0 (n Bytes)
UFI
ACK RXOUTB0
C51
Endpoint FIFO bank 0 - Read Byte 1 OUT DATA1 (m Bytes) ACK Endpoint FIFO bank 0 - Read Byte 2 Endpoint FIFO bank 0 - Read Byte n Clear RXOUTB0 OUT DATA0 (p Bytes) ACK RXOUTB1 Endpoint FIFO bank 1 - Read Byte 1 Endpoint FIFO bank 1 - Read Byte 2 Endpoint FIFO bank 1 - Read Byte m Clear RXOUTB1 RXOUTB0 Endpoint FIFO bank 0 - Read Byte 1 Endpoint FIFO bank 0 - Read Byte 2 Endpoint FIFO bank 0 - Read Byte p Clear RXOUTB0
An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt packets. When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data Bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUB0 bit to allow the USB controller to accept the next OUT packet on the endpoint bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each OUT requests on the bank 0 endpoint FIFO. When a new valid OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each OUT requests on the bank 1 endpoint FIFO. The RXOUTB0 and RXOUTB1 bits are, alternatively, set by the USB controller at each new valid packet receipt. The firmware has to clear one of these 2 bits after having read all the data FIFO to allow a new valid packet to be stored in the corresponding bank. A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been released by the firmware.
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If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won't be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Bulk/Interrupt IN Transactions in Standard Mode Figure 64. Bulk/Interrupt IN Transactions in Standard Mode
HOST
IN NAK
UFI
C51
Endpoint FIFO Write Byte 1 Endpoint FIFO Write Byte 2 Endpoint FIFO Write Byte n Set TXRDY
IN DATA0 (n Bytes) ACK TXCMPL Clear TXCMPL Endpoint FIFO Write Byte 1
An endpoint should be first enabled and configured before being able to send Bulk or Interrupt packets. The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning this endpoint. To send a Zero Length Packet, the firmware should set the TXRDY bit without writing any data into the endpoint FIFO. Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK handshake for each IN requests. To cancel the sending of this packet, the firmware has to reset the TXRDY bit. The packet stored in the endpoint FIFO is then cleared and a new packet can be written and sent. When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with new data. The firmware should never write more Bytes than supported by the endpoint FIFO. All USB retry mechanisms are automatically managed by the USB controller.
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Bulk/Interrupt IN Transactions in Ping-pong Mode
Figure 65. Bulk/Interrupt IN transactions in Ping-pong mode
HOST
IN
UFI
C51
Endpoint FIFO bank 0 - Write Byte 1 Endpoint FIFO bank 0 - Write Byte 2
NACK Endpoint FIFO bank 0 - Write Byte n Set TXRDY IN DATA0 (n Bytes) ACK Endpoint FIFO bank 1 - Write Byte m TXCMPL Clear TXCMPL Set TXRDY IN DATA1 (m Bytes) ACK Endpoint FIFO bank 0 - Write Byte 1 Endpoint FIFO bank 0 - Write Byte 2 Endpoint FIFO bank 0 - Write Byte p TXCMPL IN DATA0 (p Bytes) ACK Clear TXCMPL Set TXRDY Endpoint FIFO bank 1 - Write Byte 1 Endpoint FIFO bank 1 - Write Byte 1 Endpoint FIFO bank 1 - Write Byte 2
An endpoint should be first enabled and configured before being able to send Bulk or Interrupt packets. The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning the endpoint. The FIFO banks are automatically switched, and the firmware can immediately write into the endpoint FIFO bank 1. When the IN packet concerning the bank 0 has been sent and acknowledged by the Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks are then automatically switched. When the IN packet concerning the bank 1 has been sent and acknowledged by the Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data. The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller will answer a NAK handshake for each IN requests concerning this bank. Note that in the example above, the firmware clears the Transmit Complete bit (TXCBulk-outMPL) before setting the Transmit Ready bit (TXRDY). This is done in order to avoid the firmware to clear at the same time the TXCMPL bit for for bank 0 and the bank 1. The firmware should never write more Bytes than supported by the endpoint FIFO.
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Control Transactions
Setup Stage The DIR bit in the UEPSTAX register should be at 0. Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate that an Out packet with a Setup PID has been received on the Control endpoint. When the RXSETUP bit has been set, all the other bits of the UEPSTAX register are cleared and an interrupt is triggered if enabled. The firmware has to read the Setup request stored in the Control endpoint FIFO before clearing the RXSETUP bit to free the endpoint FIFO for the next transaction. Data Stage: Control Endpoint Direction The data stage management is similar to Bulk management. A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and OUT. All other endpoint types are managed as half-duplex endpoint: IN or OUT. The firmware has to specify the control endpoint direction for the data stage using the DIR bit in the UEPSTAX register. * If the data stage consists of INs, the firmware has to set the DIR bit in the UEPSTAX register before writing into the FIFO and sending the data by setting to 1 the TXRDY bit in the UEPSTAX register. The IN transaction is complete when the TXCMPL has been set by the hardware. The firmware should clear the TXCMPL bit before any other transaction. If the data stage consists of OUTs, the firmware has to leave the DIR bit at 0. The RXOUTB0 bit is set by hardware when a new valid packet has been received on the endpoint. The firmware must read the data stored into the FIFO and then clear the RXOUTB0 bit to reset the FIFO and to allow the next transaction.
*
To send a STALL handshake, see "STALL Handshake" on page 94. Status Stage The DIR bit in the UEPSTAX register should be reset at 0 for IN and OUT status stage. The status stage management is similar to Bulk management. * For a Control Write transaction or a No-Data Control transaction, the status stage consists of a IN Zero Length Packet (see "Bulk/Interrupt IN Transactions in Standard Mode" on page 89). To send a STALL handshake, see "STALL Handshake" on page 94. For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see "Bulk/Interrupt OUT Transactions in Standard Mode" on page 87).
*
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Isochronous Transactions
Isochronous OUT Transactions in Standard Mode An endpoint should be first enabled and configured before being able to receive Isochronous packets. When an OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corre Bulk-outsponding endpoint, store the number of data Bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt. When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUTB0 bit to allow the USB controller to store the next OUT packet data into the endpoint FIFO. Until the RXOUTB0 bit has been cleared by the firmware, the data sent by the Host at each OUT transaction will be lost. If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will store only the remaining Bytes into the FIFO. If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won't be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Isochronous OUT Transactions in Ping-pong Mode An endpoint should be first enabled and configured before being able to receive Isochronous packets. When a OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data Bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt. When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUB0 bit to allow the USB controller to store the next OUT packet data into the endpoint FIFO bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware, the data sent by the Host on the bank 0 endpoint FIFO will be lost. If the RXOUTB0 bit is cleared while the Host is sending data on the endpoint bank 0, the USB controller will store only the remaining Bytes into the FIFO. When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firmware, the data sent by the Host on the bank 1 endpoint FIFO will be lost. The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new packet receipt. The firmware has to clear one of these 2 bits after having read all the data FIFO to allow a new packet to be stored in the corresponding bank.
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If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won't be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Isochronous IN Transactions in Standard Mode An endpoint should be first enabled and configured before being able to send Isochronous packets. The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning this endpoint. If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB controller. When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with new data. The firmware should never write more Bytes than supported by the endpoint FIFO Isochronous IN Transactions in Ping-pong Mode An endpoint should be first enabled and configured before being able to send Isochronous packets. The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning the endpoint. The FIFO banks are automatically switched, and the firmware can immediately write into the endpoint FIFO bank 1. If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB controller. When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks are then automatically switched. When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data. The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller won't send anything at each IN requests concerning this bank. The firmware should never write more Bytes than supported by the endpoint FIFO.
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Miscellaneous
USB Reset The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been detected on the USB bus. This triggers a USB interrupt if enabled. The USB controller is still enabled, but all the USB registers are reset by hardware. The firmware should clear the EORINT bit to allow the next USB reset detection. This function is only available for Control, Bulk, and Interrupt endpoints. The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake at the next request of the Host on the endpoint selected with the UEPNUM register. The RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first resseted to 0. The bit STLCRC is set at 1 by the USB controller when a STALL has been sent. This triggers an interrupt if enabled. The firmware should clear the STALLRQ and STLCRC bits after each STALL sent. The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is received on a CONTROL type endpoint. Important note: when a Clear Halt Feature occurs for an endpoint, the firmware should reset this endpoint using the UEPRST resgister in order to reset the data toggle management. Start of Frame Detection The SOFINT bit in the USBINT register is set when the USB controller detects a Start Of Frame PID. This triggers an interrupt if enabled. The firmware should clear the SOFINT bit to allow the next Start of Frame detection. When receiving a Start Of Frame, the frame number is automatically stored in the UFNUML and UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of the last Start Of Frame is valid (CRCOK set at 1) or corrupted (CRCERR set at 1). The UFNUML and UFNUMH registers are automatically updated when receiving a new Start of Frame. The Data Toggle bit is set by hardware when a DATA0 packet is received and accepted by the USB controller and cleared by hardware when a DATA1 packet is received and accepted by the USB controller. This bit is reset when the firmware resets the endpoint FIFO using the UEPRST register. For Control endpoints, each SETUP transaction starts with a DATA0 and data toggling is then used as for Bulk endpoints until the end of the Data stage (for a control write transfer). The Status stage completes the data transfer with a DATA1 (for a control read transfer). For Isochronous endpoints, the device firmware should ignore the data-toggle.
STALL Handshake
Frame Number
Data Toggle Bit
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Suspend/Resume Management
Suspend The Suspend state can be detected by the USB controller if all the clocks are enabled and if the USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for more than 3 ms. This triggers a USB interrupt if enabled. In order to reduce current consumption, the firmware can stop the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active. The stop of the 48 MHz clock from the PLL should be done in the following order: 1. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUSPCLK bit in the USBCON register. 2. Disable the PLL by clearing the PLLEN bit in the PLLCON register. Resume When the USB controller is in Suspend state, the Resume detection is active even if all the clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by hardware when a non-idle state occurs on the USB bus. This triggers an interrupt if enabled. This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is then executed. The firmware should first enable the 48 MHz generation and then reset to 0 the SUSPCLK bit in the USBCON register if needed. The firmware has to clear the SPINT bit in the USBINT register before any other USB operation in order to wake up the USB controller from its Suspend mode. The USB controller is then re-activated. Figure 66. Example of a Suspend/Resume management USB Controller Init
SPINT Detection of a SUSPEND State Set SUSPCLK Disable PLL
Microcontroller in Power-down
WUPCPU Detection of a RESUME State Enable PLL Clear SUSPCLK Clear SPINT Bit Clear WUPCPU Bit
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Upstream Resume
A USB device can be allowed by the Host to send an upstream resume for Remote Wake-up purpose. When the USB controller receives the SET_FEATURE request: DEVICE_REMOTE_WAKEUP, the firmware should set to 1 the RMWUPE bit in the USBCON register to enable this functionality. RMWUPE value should be 0 in the other cases. If the device is in SUSPEND mode, the USB controller can send an upstream resume by clearing first the SPINT bit in the USBINT register and by setting then to 1 the SDRMWUP bit in the USBCON register. The USB controller sets to 1 the UPRSM bit in the USBCON register. All clocks must be enabled first. The Remote Wake is sent only if the USB bus was in Suspend state for at least 5ms. When the upstream resume is completed, the UPRSM bit is reset to 0 by hardware. The firmware should then clear the SDRMWUP bit.
Figure 67. Example of REMOTE WAKEUP Management USB Controller Init
SET_FEATURE: DEVICE_REMOTE_WAKEUP Set RMWUPE SPINT Detection of a SUSPEND state Suspend Management need USB resume
enable clocks Clear SPINT UPRSM = 1 UPRSM upstream RESUME sent Clear SDRMWUP Set SDMWUP
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USB Interrupt System
Interrupt System Priorities Figure 68. USB Interrupt Control System
D+ D-
USB Controller EUSB
IE1.6
00 01 10 11
EA
IE0.7
Interrupt Enable
IPH/L Priority Enable
Lowest Priority Interrupts
Table 1. Priority Levels
IPHUSB 0 0 1 1 IPLUSB 0 1 0 1 USB Priority Level 0..................Lowest 1 2 3..................Highest
USB Interrupt Control System
As shown in Figure 69, many events can produce a USB interrupt: * * * TXCMPL: Transmitted In Data (Table 96 on page 103). This bit is set by hardware when the Host accept a In packet. RXOUTB0: Received Out Data Bank 0 (Table 96 on page 103). This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 0. RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (Table 96 on page 103). This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 1. RXSETUP: Received Setup (Table 96 on page 103). This bit is set by hardware when an SETUP packet is accepted by the endpoint. STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table 96 on page 103). This bit is set by hardware when a STALL handshake has been sent as requested by STALLRQ, and is reset by hardware when a SETUP packet is received. SOFINT: Start of Frame Interrupt (Table 92 on page 100). This bit is set by hardware when a USB start of frame packet has been received. WUPCPU: Wake-Up CPU Interrupt (Table 92 on page 100). This bit is set by hardware when a USB resume is detected on the USB bus, after a SUSPEND state. SPINT: Suspend Interrupt (Table 92 on page 100). This bit is set by hardware when a USB suspend is detected on the USB bus.
* *
* * *
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Figure 69. USB Interrupt Control Block Diagram Endpoint X (X = 0..2)
TXCMP
UEPSTAX.0
RXOUTB0
UEPSTAX.1
RXOUTB1
UEPSTAX.6
EPXINT
UEPINT.X
RXSETUP
UEPSTAX.2
EPXIE
UEPIEN.X
STLCRC
UEPSTAX.3
NAKOUT
UEPCONX.5
NAKIN
UEPCONX.4
NAKIEN
UEPCONX.6
WUPCPU
USBINT.5
EUSB
EWUPCPU
USBIEN.5 IE1.6
EORINT
USBINT.4
EEORINT
USBIEN.4
SOFINT
USBINT.3
ESOFINT
USBIEN.3
SPINT
USBINT.0
ESPINT
USBIEN.0
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Registers
Table 90. USBCON Register USBCON (S:BCh) - USB Global Control Register
7 USBE Bit Number 6 SUSPCLK 5 SDRMWUP 4 3 UPRSM 2 RMWUPE 1 CONFG 0 FADDEN
Bit Mnemonic Description USB Enable Bit Set this bit to enable the USB controller. Clear this bit to disable and reset the USB controller, to disable the USB transceiver an to disable the USB controllor clock inputs. Suspend USB Clock Bit Set to disable the 48 MHz clock input (Resume Detection is still active). Clear to enable the 48 MHz clock input.
7
USBE
6
SUSPCLK
5
Send Remote Wake-Up Bit Set to force an external interrupt on the USB controller for Remote Wake UP purpose. SDRMWUP An upstream resume is send only if the bit RMWUPE is set, all USB clocks are enabled AND the USB bus was in SUSPEND state for at least 5 ms. See UPRSM below. Cleared by software. Reserved The value read from this bit is always 0. Do not set this bit. Upstream Resume Bit (read only) Set by hardware when SDRMWUP has been set and if RMWUPE is enabled. Cleared by hardware after the upstream resume has been sent. Remote Wake-Up Enable Bit Set to enabled request an upstream resume signaling to the host. Clear after the upstream resume has been indicated by RSMINPR. Note: Do not set this bit if the host has not set the DEVICE_REMOTE_WAKEUP feature for the device. Configuration Bit This bit should be set by the device firmware after a SET_CONFIGURATION request with a non-zero value has been correctly processed. It should be cleared by the device firmware when a SET_CONFIGURATION request with a zero value is received. It is cleared by hardware on hardware reset or when an USB reset is detected on the bus (SE0 state for at least 32 Full Speed bit times: typically 2.7 s). Function Address Enable Bit This bit should be set by the device firmware after a successful status phase of a SET_ADDRESS transaction. It should not be cleared afterwards by the device firmware. It is cleared by hardware on hardware reset or when an USB reset is received (see above). When this bit is cleared, the default function address is used (0).
4
3
UPRSM
2
RMWUPE
1
CONFG
0
FADDEN
Reset Value = 0000 0000b
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Table 91. USBADDR Register USBADDR (S:C6h) - USB Address Register
7 FEN Bit Number 6 UADD6 5 UADD5 4 UADD4 3 UADD3 2 UADD2 1 UADD1 0 UADD0
Bit Mnemonic Description Function Enable Bit Set to enable the function. The device firmware should set this bit after it has received a USB reset and participate in the following configuration process with the default address (FEN is reset to 0). Cleared by hardware at power-up, should not be cleared by the device firmware once set. USB Address Bits This field contains the default address (0) after power-up or USB bus reset. It should be written with the value set by a SET_ADDRESS request received by the device firmware.
7
FEN
6-0
UADD6:0
Reset Value = 0000 0000b Table 92. USBINT Register USBINT (S:BDh) - USB Global Interrupt Register
7 Bit Number 7-6 6 5 WUPCPU 4 EORINT 3 SOFINT 2 1 0 SPINT
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Wake Up CPU Interrupt Flag Set by hardware when the USB controller is in SUSPEND state and is reactivated by a non-idle signal from USB line (not by an upstream resume). This triggers a USB interrupt when EWUPCPU is set in the USBIEN. Cleared by software after re-enabling all USB clocks. End of Reset Interrupt Flag Set by hardware when a End of Reset has been detected by the USB controller. This triggers a USB interrupt when EEORINT is set in USBIEN. Cleared by software. Start of Frame Interrupt Flag Set by hardware when an USB Start of Frame packet (SOF) has been properly received. This triggers a USB interrupt when ESOFINT is set in USBIEN. Cleared by software. Reserved The value read from these bits is always 0. Do not set these bits. Suspend Interrupt Flag Set by hardware when a USB Suspend (Idle bus for three frame periods: a J state for 3 ms) is detected. This triggers a USB interrupt when ESPINT is set in USBIEN. Cleared by software.
5
WUPCPU
4
EORINT
3
SOFINT
2-1
-
0
SPINT
Reset Value = 0000 0000b
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Table 93. USBIEN Register USBIEN (S:BEh) - USB Global Interrupt Enable Register
7 Bit Number 7-6 6 5 EWUPCPU 4 EEORINT 3 ESOFINT 2 1 0 ESPINT
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits.
5
Wake Up CPU Interrupt Enable Bit EWUPCPU Set to enable the Wake Up CPU interrupt. Clear to disable the Wake Up CPU interrupt. End Of Reset Interrupt Enable Bit Set to enable the End Of Reset interrupt. This bit is set after reset. Clear to disable End Of Reset interrupt. Start Of Frame Interrupt Enable Bit Set to enable the SOF interrupt. Clear to disable the SOF interrupt. Reserved The value read from these bits is always 0. Do not set these bits. Suspend Interrupt Enable Bit Set to enable Suspend interrupt. Clear to disable Suspend interrupt.
4
EEOFINT
3
ESOFINT
2-1
-
0
ESPINT
Reset Value = 0001 0000b Table 94. UEPNUM Register UEPNUM (S:C7h) - USB Endpoint Number
7 Bit Number 7-2 6 5 4 3 2 1 EPNUM1 0 EPNUM0
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits.
1-0
Endpoint Number Bits EPNUM1:0 Set this field with the number of the endpoint which should be accessed when reading or writing to registers UEPSTAX, UEPDATX, UBYCTX or UEPCONX.
Reset Value = 0000 0000b
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Table 95. UEPCONX Register UEPCONX (S:D4h) - USB Endpoint X Control Register (X = EPNUM set in UEPNUM)
7 EPEN Bit Number 6 NAKIEN 5 NAKOUT 4 NAKIN 3 DTGL 2 EPDIR 1 EPTYPE1 0 EPTYPE0
Bit Mnemonic Description Endpoint Enable Bit Set to enable the endpoint according to the device configuration. Endpoint 0 should always be enabled after a hardware or USB bus reset and participate in the device configuration. Clear to disable the endpoint according to the device configuration. NAK Interrupt enable Set this bit to enable NAK IN or NAK OUT interrupt. Clear this bit to disable NAK IN or NAK OUT Interrupt. NAK OUT received This bit is set by hardware when an NAK handshake has been sent in response of a OUT request from the Host. This triggers a USB interrupt when NAKIEN is set. This bit should be cleared by software. NAK IN received This bit is set by hardware when an NAK handshake has been sent in response of a IN request from the Host. This triggers a USB interrupt when NAKIEN is set. This bit should be cleared by software. Data Toggle Status Bit (Read-only) Set by hardware when a DATA1 packet is received. Cleared by hardware when a DATA0 packet is received. Endpoint Direction Bit Set to configure IN direction for Bulk, Interrupt and Isochronous endpoints. Clear to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. This bit has no effect for Control endpoints.
7
EPEN
6
NAKIEN
5
NAKOUT
4
NAKIN
3
DTGL
2
EPDIR
1-0
Endpoint Type Bits Set this field according to the endpoint configuration (Endpoint 0 should always be configured as Control): EPTYPE1:0 00 Control endpoint 01 Isochronous endpoint 10 Bulk endpoint 11 Interrupt endpoint
Reset Value = 1000 0000b
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Table 96. UEPSTAX Register
UEPSTAX (S:CEh) - USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM)
7 DIR Bit Number 6 RXOUTB1 5 STALLRQ 4 TXRDY 3 STLCRC 2 RXSETUP 1 RXOUTB0 0 TXCMP
Bit Mnemonic Description Control Endpoint Direction Bit This bit is relevant only if the endpoint is configured in Control type. Set for the data stage. Clear otherwise.
7
DIR
Note: This bit should be configured on RXSETUP interrupt before any other bit is changed. This also determines the status phase (IN for a control write and OUT for a control read). This bit should be cleared for status stage of a Control Out transaction. Received OUT Data Bank 1 for Endpoints 1 and 2 (Ping-pong mode) This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 1 (only in Ping-pong mode). Then, the endpoint interrupt is triggered if enabled and all the following OUT packets to the endpoint bank 1 are rejected (NAK'ed) until this bit has been cleared, excepted for Isochronous Endpoints. This bit should be cleared by the device firmware after reading the OUT data from the endpoint FIFO.
6
RXOUTB1
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Bit Number 5
Bit Mnemonic Description STALLRQ Stall Handshake Request Bit Set to send a STALL answer to the host for the next handshake. Clear otherwise. TX Packet Ready Control Bit Set after a packet has been written into the endpoint FIFO for IN data transfers. Data should be written into the endpoint FIFO only after this bit has been cleared. Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet, which is generally recommended and may be required to terminate a transfer when the length of the last data packet is equal to MaxPacketSize (e.g. for control read transfers). Cleared by hardware, as soon as the packet has been sent for Isochronous endpoints, or after the host has acknowledged the packet for Control, Bulk and Interrupt endpoints. Stall Sent Interrupt Flag/CRC Error Interrupt Flag For Control, Bulk and Interrupt Endpoints: Set by hardware after a STALL handshake has been sent as requested by STALLRQ. Then, the endpoint interrupt is triggered if enabled in UEPIEN. Cleared by hardware when a SETUP packet is received (see RXSETUP). For Isochronous Endpoints: Set by hardware if the last data received is corrupted (CRC error on data). Then, the endpoint interrupt is triggered if enabled in UEPIEN. Cleared by hardware when a non corrupted data is received. Received SETUP Interrupt Flag Set by hardware when a valid SETUP packet has been received from the host. Then, all the other bits of the register are cleared by hardware and the endpoint interrupt is triggered if enabled in UEPIEN. Clear by software after reading the SETUP data from the endpoint FIFO. Received OUT Data Bank 0 (see also RXOUTB1 bit for Ping-pong Endpoints) This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 0. Then, the endpoint interrupt is triggered if enabled and all the following OUT packets to the endpoint bank 0 are rejected (NAK'ed) until this bit has been cleared, excepted for Isochronous Endpoints. However, for control endpoints, an early SETUP transaction may overwrite the content of the endpoint FIFO, even if its Data packet is received while this bit is set. This bit should be cleared by the device firmware after reading the OUT data from the endpoint FIFO. Transmitted IN Data Complete Interrupt Flag Set by hardware after an IN packet has been transmitted for Isochronous endpoints and after it has been accepted (ACK'ed) by the host for Control, Bulk and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled in UEPIEN. Clear by software before setting again TXRDY.
4
TXRDY
3
STLCRC
2
RXSETUP
1
RXOUTB0
0
TXCMP
Reset Value = 0000 0000b
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Table 97. UEPRST Register UEPRST (S:D5h) - USB Endpoint FIFO Reset Register
7 Bit Number 7-3 6 5 4 3 2 EP2RST 1 EP1RST 0 EP0RST
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Endpoint 2 FIFO Reset Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Endpoint 1 FIFO Reset Set and clear to reset the endpoint 1 FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Endpoint 0 FIFO Reset Set and clear to reset the endpoint 0 FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received.
2
EP2RST
1
EP1RST
0
EP0RST
Reset Value = 0000 0000b Table 98. UEPINT Register UEPINT (S:F8h Read-only) - USB Endpoint Interrupt Register
7 Bit Number 7-3 6 5 4 3 2 EP2INT 1 EP1INT 0 EP0INT
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Endpoint 2 Interrupt Flag Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 2 interrupt is enabled in UEPIEN. Must be cleared by software. Endpoint 1 Interrupt Flag Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 1 interrupt is enabled in UEPIEN. Must be cleared by software. Endpoint 0 Interrupt Flag Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 0 interrupt is enabled in UEPIEN. Must be cleared by software.
2
EP2INT
1
EP1INT
0
EP0INT
Reset Value = 0000 0000b
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Table 99. UEPIEN Register
UEPIEN (S:C2h) - USB Endpoint Interrupt Enable Register
7 Bit Number 7-3 6 5 4 3 2 EP2INTE 1 EP1INTE 0 EP0INTE
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Endpoint 2 Interrupt Enable Bit Set to enable the interrupts for endpoint 2. Clear this bit to disable the interrupts for endpoint 2. Endpoint 1 Interrupt Enable Bit Set to enable the interrupts for the endpoint 1. Clear to disable the interrupts for the endpoint 1. Endpoint 0 Interrupt Enable Bit Set to enable the interrupts for the endpoint 0. Clear to disable the interrupts for the endpoint 0.
2
EP2INTE
1
EP1INTE
0
EP0INTE
Reset Value = 0000 0000b Table 100. UEPDATX Register
UEPDATX (S:CFh) - USB Endpoint X FIFO Data Register (X = EPNUM set in UEPNUM)
7 FDAT7 Bit Number 6 FDAT6 5 FDAT5 4 FDAT4 3 FDAT3 2 FDAT2 1 FDAT1 0 FDAT0
Bit Mnemonic Description Endpoint X FIFO Data Data Byte to be written to FIFO or data Byte to be read from the FIFO, for the Endpoint X (see EPNUM).
7-0
FDAT7:0
Reset Value = XXh
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Table 101. UBYCTX Register UBYCTX (S:E2h) - USB Endpoint X Byte Count Register (X = EPNUM set in UEPNUM)
7 Bit Number 7 6 BYCT6 5 BYCT5 4 BYCT4 3 BYCT3 2 BYCT2 1 BYCT1 0 BYCT0
Bit Mnemonic Description Reserved The value read from this bits is always 0. Do not set this bit. Byte Count Byte count of a received data packet. This Byte count is equal to the number of data Bytes received after the Data PID.
6-0
BYCT7:0
Reset Value = 0000 0000b Table 102. UFNUML Register UFNUML (S:BAh, Read-only) - USB Frame Number Low Register
7 FNUM7 Bit Number 7-0 6 FNUM6 5 FNUM5 4 FNUM4 3 FNUM3 2 FNUM2 1 FNUM1 0 FNUM0
Bit Mnemonic Description FNUM7:0 Frame Number Lower 8 bits of the 11-bit Frame Number.
Reset Value = 00h
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Table 103. UFNUMH Register UFNUMH (S:BBh, Read-only) - USB Frame Number High Register
7 Bit Number 7-3 6 5 CRCOK 4 CRCERR 3 2 FNUM10 1 FNUM9 0 FNUM8
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Frame Number CRC OK Bit Set by hardware after a non corrupted Frame Number in Start of Frame Packet is received. Updated after every Start Of Frame packet reception. Note: The Start Of Frame interrupt is generated just after the PID receipt. Frame Number CRC Error Bit Set by hardware after a corrupted Frame Number in Start of Frame Packet is received. Updated after every Start Of Frame packet reception. Note: The Start Of Frame interrupt is generated just after the PID receipt.
5
CRCOK
4
CRCERR
3
-
Reserved The value read from this bits is always 0. Do not set this bit.
2-0
Frame Number FNUM10:8 Upper 3 bits of the 11-bit Frame Number. It is provided in the last received SOF packet. FNUM does not change if a corrupted SOF is received.
Reset Value = 00h Table 104. USBCLK Register USBCLK (S:EAh) - USB Clock Divider Register
7 Bit Number 7-2 6 5 4 3 2 1 USBCD1 0 USBCD0
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. USB Controller Clock Divider 2-bit divider for USB controller clock generation.
1-0
USBCD1:0
Reset Value = 0000 0000b
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MultiMedia Card Controller
Card Concept
Card Signals The AT8xC51SND1C implements a MultiMedia Card (MMC) controller. The MMC is used to store MP3 encoded audio files in removable Flash memory cards that can be easily plugged or removed from the application. The basic MultiMedia Card concept is based on transferring data via a minimum number of signals. The communication signals are: * * CLK: with each cycle of this signal a one bit transfer on the command and data lines is done. The frequency may vary from zero to the maximum clock frequency. CMD: is a bi-directional command channel used for card initialization and data transfer commands. The CMD signal has 2 operation modes: open-drain for initialization mode and push-pull for fast command transfer. Commands are sent from the MultiMedia Card bus master to the card and responses from the cards to the host. DAT: is a bi-directional data channel. The DAT signal operates in push-pull mode. Only one card or the host is driving this signal at a time.
*
Card Registers
Within the card interface five registers are defined: OCR, CID, CSD, RCA and DSR. These can be accessed only by the corresponding commands. The 32-bit Operation Conditions Register (OCR) stores the VDD voltage profile of the card. The register is optional and can be read only. The 128-bit wide CID register carries the card identification information (Card ID) used during the card identification procedure. The 128-bit wide Card-Specific Data register (CSD) provides information on how to access the card contents. The CSD defines the data format, error correction type, maximum data access time, data transfer speed, and whether the DSR register can be used. The 16-bit Relative Card Address register (RCA) carries the card address assigned by the host during the card identification. This address is used for the addressed host-card communication after the card identification procedure. The 16-bit Driver Stage Register (DSR) can be optionally used to improve the bus performance for extended operating conditions (depending on parameters like bus length, transfer rate or number of cards).
Bus Concept
The MultiMedia Card bus is designed to connect either solid-state mass-storage memory or I/O-devices in a card format to multimedia applications. The bus implementation allows the coverage of application fields from low-cost systems to systems with a fast data transfer rate. It is a single master bus with a variable number of slaves. The MultiMedia Card bus master is the bus controller and each slave is either a single mass storage card (with possibly different technologies such as ROM, OTP, Flash etc.) or an I/O-card with its own controlling unit (on card) to perform the data transfer. The MultiMedia Card bus also includes power connections to supply the cards. The bus communication uses a special protocol (MultiMedia Card bus protocol) which is applicable for all devices. Therefore, the payload data transfer between the host and the cards can be bi-directional.
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Bus Lines
The MultiMedia Card bus architecture requires all cards to be connected to the same set of lines. No card has an individual connection to the host or other devices, which reduces the connection costs of the MultiMedia Card system. The bus lines can be divided into three groups: * * * Power supply: VSS1 and VSS2, VDD - used to supply the cards. Data transfer: MCMD, MDAT - used for bi-directional communication. Clock: MCLK - used to synchronize data transfer across the bus.
Bus Protocol
After a power-on reset, the host must initialize the cards by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: * * Command: a command is a token which starts an operation. A command is transferred serially from the host to the card on the MCMD line. Response: a response is a token which is sent from an addressed card (or all connected cards) to the host as an answer to a previously received command. It is transferred serially on the MCMD line. Data: data can be transferred from the card to the host or vice-versa. Data is transferred serially on the MDAT line.
*
Card addressing is implemented using a session address assigned during the initialization phase, by the bus controller to all currently connected cards. Individual cards are identified by their CID number. This method requires that every card will have an unique CID number. To ensure uniqueness of CIDs the CID register contains 24 bits (MID and OID fields) which are defined by the MMCA. Every card manufacturers is required to apply for an unique MID (and optionally OID) number. MultiMedia Card bus data transfers are composed of these tokens. One data transfer is a bus operation. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token, the others transfer their information directly within the command or response structure. In this case no data token is present in an operation. The bits on the MDAT and the MCMD lines are transferred synchronous to the host clock. 2 types of data transfer commands are defined: * Sequential commands: These commands initiate a continuous data stream, they are terminated only when a stop command follows on the MCMD line. This mode reduces the command overhead to an absolute minimum. Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the MCMD line similarly to the stream read.
*
Figure 70 through Figure 74 show the different types of operations, on these figures, grayed tokens are from host to card(s) while white tokens are from card(s) to host. Figure 70. Sequential Read Operation
Stop Command
MCMD MDAT
Command
Response Data Stream
Data Transfer Operation
Command
Response
Data Stop Operation
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Figure 71. (Multiple) Block Read Operation
Stop Command
MCMD MDAT
Command
Response
Command
Response
Data Block CRC Data Block CRC Data Block CRC
Block Read Operation Multiple Block Read Operation Data Stop Operation
As shown in Figure 72 and Figure 73 the data write operation uses a simple busy signalling of the write operation duration on the data line (MDAT). Figure 72. Sequential Write Operation
Stop Command
MCMD MDAT
Command
Response Data Stream
Data Transfer Operation
Command
Response Busy
Data Stop Operation
Figure 73. Multiple Block Write Operation
Stop Command
MCMD MDAT
Command
Response Data Block CRC Status Busy
Block Write Operation Multiple Block Write Operation
Command
Response
Data Block CRC Status Busy
Data Stop Operation
Figure 74. No Response and No Data Operation
MCMD MDAT
No Response Operation No Data Operation
Command
Command
Response
Command Token Format
As shown in Figure 75, commands have a fixed code length of 48 bits. Each command token is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit: a high level on MCMD line. The command content is preceded by a Transmission bit: a high level on MCMD line for a command token (host to card) and succeeded by a 7 - bit CRC so that transmission errors can be detected and the operation may be repeated. Command content contains the command index and address information or parameters.
Figure 75. Command Token Format
0 1 Content
Total Length = 48 bits
CRC
1
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Table 105. Command Token Format
Bit Position Width (Bits) Value 47 1 `0' Start bit 46 1 `1' Transmission bit 45:40 6 Command Index 39:8 32 Argument 7:1 7 CRC7 0 1 `1' End bit
Description
Response Token Format
There are five types of response tokens (R1 to R5). As shown in Figure 76, responses have a code length of 48 bits or 136 bits. A response token is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit: a high level on MCMD line. The command content is preceded by a Transmission bit: a low level on MCMD line for a response token (card to host) and succeeded (R1,R2,R4,R5) or not (R3) by a 7 - bit CRC. Response content contains mirrored command and status information (R1 response), CID register or CSD register (R2 response), OCR register (R3 response), or RCA register (R4 and R5 response). Figure 76. Response Token Format
R1, R4, R5 0 0 Content
Total Length = 48 bits
CRC
1
R3
0
0
Content
Total Length = 48 bits
1
R2
0
0
Content = CID or CSD
Total Length = 136 bits
CRC
1
Table 106. R1 Response Format (Normal Response)
Bit Position Width (bits) Value 47 1 `0' Start bit 46 1 `0' Transmission bit 45:40 6 Command Index 39:8 32 Card Status 7:1 7 CRC7 0 1 `1' End bit
Description
Table 107. R2 Response Format (CID and CSD registers)
Bit Position Width (bits) Value 135 1 `0' Start bit 134 1 `0' Transmission bit [133:128] 6 `111111' Reserved [127:1] 32 Argument 0 1 `1' End bit
Description
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Table 108. R3 Response Format (OCR Register)
Bit Position Width (bits) Value 47 1 `0' Start bit 46 1 `0' Transmission bit [45:40] 6 `111111' Reserved [39:8] 32 OCR register [7:1] 7 `1111111' Reserved 0 1 `1' End bit
Description
Table 109. R4 Response Format (Fast I/O)
Bit Position Width (bits) Value 47 1 `0' Start bit 46 1 `0' Transmission bit [45:40] 6 `100111' Command Index [39:8] 32 Argument [7:1] 7 CRC7 0 1 `1' End bit
Description
Table 110. R5 Response Format
Bit Position Width (bits) Value 47 1 `0' Start bit 46 1 `0' Transmission bit [45:40] 6 `101000' Command Index [39:8] 32 Argument [7:1] 7 CRC7 0 1 `1' End bit
Description
Data Packet Format
There are 2 types of data packets: stream and block. As shown in Figure 77, stream data packets have an indeterminate length while block packets have a fixed length depending on the block length. Each data packet is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit: a high level on MCMD line. Due to the fact that there is no predefined end in stream packets, CRC protection is not included in this case. The CRC protection algorithm for block data is a 16-bit CCITT polynomial. Figure 77. Data Token Format
Sequential Data Block Data 0 0 Content Content
Block Length
1 CRC 1
Clock Control
The MMC bus clock signal can be used by the host to turn the cards into energy saving mode or to control the data flow (to avoid under-run or over-run conditions) on the bus. The host is allowed to lower the clock frequency or shut it down. There are a few restrictions the host must follow: * The bus frequency can be changed at any time (under the restrictions of maximum data transfer frequency, defined by the cards, and the identification frequency defined by the specification document). It is an obvious requirement that the clock must be running for the card to output data or response tokens. After the last MultiMedia Card bus transaction, the host is
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required, to provide 8 (eight) clock cycles for the card to complete the operation before shutting down the clock. Following is a list of the various bus transactions: * * * * * A command with no response. 8 clocks after the host command End bit. A command with response. 8 clocks after the card command End bit. A read data transaction. 8 clocks after the End bit of the last data block. A write data transaction. 8 clocks after the CRC status token. The host is allowed to shut down the clock of a "busy" card. The card will complete the programming operation regardless of the host clock. However, the host must provide a clock edge for the card to turn off its busy signal. Without a clock edge the card (unless previously disconnected by a deselect command-CMD7) will force the MDAT line down, forever.
Description
The MMC controller interfaces to the C51 core through the following eight special function registers: MMCON0, MMCON1, MMCON2, the three MMC control registers (see Table 112 to Table 120); MMSTA, the MMC status register (see Table 115); MMINT, the MMC interrupt register (see Table 116); MMMSK, the MMC interrupt mask register (see Table 117); MMCMD, the MMC command register (see Table 118); MMDAT, the MMC data register (see Table 119); and MMCLK, the MMC clock register (see Table 120). As shown in Figure 78, the MMC controller is divided in four blocks: the clock generator that handles the MCLK (formally the MMC CLK) output to the card, the command line controller that handles the MCMD (formally the MMC CMD) line traffic to or from the card, the data line controller that handles the MDAT (formally the MMC DAT) line traffic to or from the card, and the interrupt controller that handles the MMC controller interrupt sources. These blocks are detailed in the following sections.
Figure 78. MMC Controller Block Diagram
MCLK
OSC CLOCK
Clock Generator
Command Line Controller Interrupt Controller
MCMD MMC Interrupt Request MDAT
Internal Bus
Data Line Controller
8
Clock Generator
The MMC clock is generated by division of the oscillator clock (FOSC) issued from the Clock Controller block as detailed in Section "Oscillator", page 12. The division factor is given by MMCD7:0 bits in MMCLK register, a value of 0x00 stops the MMC clock. Figure 79 shows the MMC clock generator and its output clock calculation formula.
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Figure 79. MMC Clock Generator and Symbol
OSC CLOCK
Controller Clock MMCLK MMCEN
MMCON2.7
OSCclk MMCclk = ---------------------------MMCD + 1
MMC CLOCK
MMCD7:0
MMC Clock
MMC Clock Symbol
As soon as MMCEN bit in MMCON2 is set, the MMC controller receives its system clock. The MMC command and data clock is generated on MCLK output and sent to the command line and data line controllers. Figure 80 shows the MMC controller configuration flow. As exposed in Section "Clock Control", page 113, MMCD7:0 bits can be used to dynamically increase or reduce the MMC clock. Figure 80. Configuration Flow
MMC Controller Configuration
Configure MMC Clock MMCLK = XXh MMCEN = 1 FLOWC = 0
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Command Line Controller
As shown in Figure 81, the command line controller is divided in 2 channels: the command transmitter channel that handles the command transmission to the card through the MCMD line and the command receiver channel that handles the response reception from the card through the MCMD line. These channels are detailed in the following sections.
Figure 81. Command Line Controller Block Diagram
TX Pointer
5-Byte FIFO MMCMD Write
Data Converter // -> Serial
CRC7 Generator
CTPTR
MMCON0.4
TX COMMAND Line Finished State Machine CFLCK
MMSTA.0
MMINT.5
EOCI MCMD
CMDEN Command Transmitter
MMCON1.0 MMSTA.2 MMSTA.1
CRC7S Data Converter Serial -> //
RESPFS
RX Pointer
17 - Byte FIFO MMCMD Read
CRC7 and Format Checker
CRPTR
MMCON0.5
RX COMMAND Line Finished State Machine RESPEN Command Receiver RFMT CRCDIS
MMINT.6
EORI
MMCON1.1 MMCON0.1 MMCON0.0
Command Transmitter
For sending a command to the card, user must load the command index (1 Byte) and argument (4 Bytes) in the command transmit FIFO using the MMCMD register. Before starting transmission by setting and clearing the CMDEN bit in MMCON1 register, user must first configure: * * * RESPEN bit in MMCON1 register to indicate whether a response is expected or not. RFMT bit in MMCON0 register to indicate the response size expected. CRCDIS bit in MMCON0 register to indicate whether the CRC7 included in the response will be computed or not. In order to avoid CRC error, CRCDIS may be set for response that do not include CRC7.
Figure 82 summarizes the command transmission flow. As soon as command transmission is enabled, the CFLCK flag in MMSTA is set indicating that write to the FIFO is locked. This mechanism is implemented to avoid command overrun. The end of the command transmission is signalled to you by the EOCI flag in MMINT register becoming set. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 124. The end of the command transmission also resets the CFLCK flag.
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User may abort command loading by setting and clearing the CTPTR bit in MMCON0 register which resets the write pointer to the transmit FIFO. Figure 82. Command Transmission Flow
Command Transmission
Load Command in Buffer MMCMD = index MMCMD = argument
Configure Response RESPEN = X RFMT = X CRCDIS = X
Transmit Command CMDEN = 1 CMDEN = 0
Command Receiver
The end of the response reception is signalled to you by the EORI flag in MMINT register. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 124. When this flag is set, 2 other flags in MMSTA register: RESPFS and CRC7S give a status on the response received. RESPFS indicates if the response format is correct or not: the size is the one expected (48 bits or 136 bits) and a valid End bit has been received, and CRC7S indicates if the CRC7 computation is correct or not. These Flags are cleared when a command is sent to the card and updated when the response has been received. User may abort response reading by setting and clearing the CRPTR bit in MMCON0 register which resets the read pointer to the receive FIFO. According to the MMC specification delay between a command and a response (formally NCR parameter) can not exceed 64 MMC clock periods. To avoid any locking of the MMC controller when card does not send its response (e.g. physically removed from the bus), user must launch a time-out period to exit from such situation. In case of timeout user may reset the command controller and its internal state machine by setting and clearing the CCR bit in MMCON2 register. This time-out may be disarmed when receiving the response.
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Data Line Controller
The data line controller is based on a 16-Byte FIFO used both by the data transmitter channel and by the data receiver channel.
Figure 83. Data Line Controller Block Diagram
MMINT.0
MMINT.2
MMSTA.3
MMSTA.4
F1EI
F1FI
DATFS
CRC16S Data Converter Serial -> //
CRC16 and Format Checker 8-Byte
TX Pointer
FIFO 1 16-Byte FIFO MMDAT 8-Byte FIFO 2
MCBI
MMINT.1
CBUSY
MMSTA.5
MDAT CRC16 Generator
DTPTR
MMCON0.6
RX Pointer
Data Converter // -> Serial
DRPTR
MMCON0.7
DATA Line Finished State Machine DFMT MBLOCK
MMCON0.3
MMINT.4
EOFI
DATEN
MMCON1.2
DATDIR
BLEN3:0
F2EI
MMINT.1
F2FI
MMINT.3
MMCON0.2
MMCON1.3 MMCON1.7:4
FIFO Implementation
The 16-Byte FIFO is based on a dual 8-Byte FIFOs managed using 2 pointers and four flags indicating the status full and empty of each FIFO. Pointers are not accessible to user but can be reset at any time by setting and clearing DRPTR and DTPTR bits in MMCON0 register. Resetting the pointers is equivalent to abort the writing or reading of data. F1EI and F2EI flags in MMINT register signal when set that respectively FIFO1 and FIFO2 are empty. F1FI and F2FI flags in MMINT register signal when set that respectively FIFO1 and FIFO2 are full. These flags may generate an MMC interrupt request as detailed in Section "Interrupt". Before sending or receiving any data, the data line controller must be configured according to the type of the data transfer considered. This is achieved using the Data Format bit: DFMT in MMCON0 register. Clearing DFMT bit enables the data stream format while setting DFMT bit enables the data block format. In data block format, user must also configure the single or multi-block mode by clearing or setting the MBLOCK bit in MMCON0 register and the block length using BLEN3:0 bits in MMCON1 according to Table 111. Figure 84 summarizes the data modes configuration flows. Table 111. Block Length Programming
BLEN3:0 BLEN = 0000 to 1011 > 1011 Block Length (Byte) Length = 2BLEN: 1 to 2048 Reserved: do not program BLEN3:0 > 1011
Data Configuration
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Figure 84. Data Controller Configuration Flows
Data Stream Configuration Data Single Block Configuration Data Multi-Block Configuration
Configure Format DFMT = 0
Configure Format DFMT = 1 MBLOCK = 0 BLEN3:0 = XXXXb
Configure Format DFMT = 1 MBLOCK = 1 BLEN3:0 = XXXXb
Data Transmitter Configuration For transmitting data to the card user must first configure the data controller in transmission mode by setting the DATDIR bit in MMCON1 register. Figure 85 summarizes the data stream transmission flows in both polling and interrupt modes while Figure 86 summarizes the data block transmission flows in both polling and interrupt modes, these flows assume that block length is greater than 16 data. Data Loading Data is loaded in the FIFO by writing to MMDAT register. Number of data loaded may vary from 1 to 16 Bytes. Then if necessary (more than 16 Bytes to send) user must wait that one FIFO becomes empty (F1EI or F2EI set) before loading 8 new data. Transmission is enabled by setting and clearing DATEN bit in MMCON1 register. Data is transmitted immediately if the response has already been received, or is delayed after the response reception if its status is correct. In both cases transmission is delayed if a card sends a busy state on the data line until the end of this busy condition. According to the MMC specification, the data transfer from the host to the card may not start sooner than 2 MMC clock periods after the card response was received (formally N WR parameter). To address all card types, this delay can be programmed using DATD1:0 bits in MMCON2 register from 3 MMC clock periods when DATD1:0 bits are cleared to 9 MMC clock periods when DATD1:0 bits are set, by step of 2 MMC clock periods. End of Transmission The end of a data frame (block or stream) transmission is signalled to you by the EOFI flag in MMINT register. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 124. In data stream mode, EOFI flag is set, after reception of the End bit. This assumes user has previously sent the STOP command to the card, which is the only way to stop stream transfer. In data block mode, EOFI flag is set, after reception of the CRC status token (see Figure 76). 2 other flags in MMSTA register: DATFS and CRC16S report a status on the frame sent. DATFS indicates if the CRC status token format is correct or not, and CRC16S indicates if the card has found the CRC16 of the block correct or not. Busy Status As shown in Figure 76 the card uses a busy token during a block write operation. This busy status is reported to you by the CBUSY flag in MMSTA register and by the MCBI flag in MMINT which is set every time CBUSY toggles, i.e. when the card enters and exits its busy state. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 124.
Data Transmission
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Figure 85. Data Stream Transmission Flows
Data Stream Transmission Data Stream Initialization Data Stream Transmission ISR
FIFOs Filling write 16 data to MMDAT
FIFOs Filling write 16 data to MMDAT
FIFO Empty? F1EI or F2EI = 1?
Start Transmission DATEN = 1 DATEN = 0
Unmask FIFOs Empty F1EM = 0 F2EM = 0
FIFO Filling write 8 data to MMDAT
FIFO Empty? F1EI or F2EI = 1?
Start Transmission DATEN = 1 DATEN = 0
No More Data To Send?
FIFO Filling write 8 data to MMDAT
Mask FIFOs Empty F1EM = 1 F2EM = 1
No More Data To Send?
Send STOP Command
Send STOP Command
b. Interrupt mode
a. Polling mode
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Figure 86. Data Block Transmission Flows
Data Block Transmission Data Block Initialization Data Block Transmission ISR
FIFOs Filling write 16 data to MMDAT
FIFOs Filling write 16 data to MMDAT
FIFO Empty? F1EI or F2EI = 1?
Start Transmission DATEN = 1 DATEN = 0
Unmask FIFOs Empty F1EM = 0 F2EM = 0
FIFO Filling write 8 data to MMDAT
FIFO Empty? F1EI or F2EI = 1?
Start Transmission DATEN = 1 DATEN = 0
No More Data To Send?
FIFO Filling write 8 data to MMDAT
Mask FIFOs Empty F1EM = 1 F2EM = 1
No More Data To Send?
b. Interrupt mode
a. Polling mode
Data Receiver Configuration To receive data from the card you must first configure the data controller in reception mode by clearing the DATDIR bit in MMCON1 register. Figure 87 summarizes the data stream reception flows in both polling and interrupt modes while Figure 88 summarizes the data block reception flows in both polling and interrupt modes, these flows assume that block length is greater than 16 Bytes. Data Reception The end of a data frame (block or stream) reception is signalled to you by the EOFI flag in MMINT register. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 124. When this flag is set, 2 other flags in MMSTA register: DATFS and CRC16S give a status on the frame received. DATFS indicates if the frame format is correct or not: a valid End bit has been received, and CRC16S indicates if the CRC16 computation is correct or not. In case of data stream CRC16S has no meaning and stays cleared. According to the MMC specification data transmission from the card starts after the access time delay (formally NAC parameter) beginning from the End bit of the read command. To avoid any locking of the MMC controller when card does not send its data (e.g. physically removed from the bus), you must launch a time-out period to exit from such situation. In case of time-out you may reset the data controller and its internal state machine by setting and clearing the DCR bit in MMCON2 register.
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This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receiving end of frame (EOFI flag set) in case of block length less than 8 data (1, 2 or 4). Data Reading Data is read from the FIFO by reading to MMDAT register. Each time one FIFO becomes full (F1FI or F2FI set), user is requested to flush this FIFO by reading 8 data.
Figure 87. Data Stream Reception Flows
Data Stream Reception Data Stream Initialization Data Stream Reception ISR
FIFO Full? F1FI or F2FI = 1?
Unmask FIFOs Full F1FM = 0 F2FM = 0
FIFO Full? F1FI or F2FI = 1?
FIFO Reading read 8 data from MMDAT
FIFO Reading read 8 data from MMDAT
No More Data To Receive?
No More Data To Receive?
Send STOP Command
Mask FIFOs Full F1FM = 1 F2FM = 1
a. Polling mode
Send STOP Command
b. Interrupt mode
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Figure 88. Data Block Reception Flows
Data Block Reception Data Block Initialization Data Block Reception ISR
Start Transmission DATEN = 1 DATEN = 0
Unmask FIFOs Full F1FM = 0 F2FM = 0
FIFO Full? F1EI or F2EI = 1?
FIFO Full? F1EI or F2EI = 1?
Start Transmission DATEN = 1 DATEN = 0
FIFO Reading read 8 data from MMDAT
FIFO Reading read 8 data from MMDAT
No More Data To Receive?
No More Data To Receive?
Mask FIFOs Full F1FM = 1 F2FM = 1
a. Polling mode
b. Interrupt mode
Flow Control
To allow transfer at high speed without taking care of CPU oscillator frequency, the FLOWC bit in MMCON2 allows control of the data flow in both transmission and reception. During transmission, setting the FLOWC bit has the following effects: * * * * MMCLK is stopped when both FIFOs become empty: F1EI and F2EI set. MMCLK is restarted when one of the FIFOs becomes full: F1EI or F2EI cleared. MMCLK is stopped when both FIFOs become full: F1FI and F2FI set. MMCLK is restarted when one of the FIFOs becomes empty: F1FI or F2FI cleared.
During reception, setting the FLOWC bit has the following effects:
As soon as the clock is stopped, the MMC bus is frozen and remains in its state until the clock is restored by writing or reading data in MMDAT.
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Interrupt
Description As shown in Figure 89, the MMC controller implements eight interrupt sources reported in MCBI, EORI, EOCI, EOFI, F2FI, F1FI, and F2EI flags in MMCINT register. These flags are detailed in the previous sections. All these sources are maskable separately using MCBM, EORM, EOCM, EOFM, F2FM, F1FM, and F2EM mask bits respectively in MMMSK register. The interrupt request is generated each time an unmasked flag is set, and the global MMC controller interrupt enable bit is set (EMMC in IEN1 register). Reading the MMINT register automatically clears the interrupt flags (acknowledgment). This implies that register content must be saved and tested interrupt flag by interrupt flag to be sure not to forget any interrupts. Figure 89. MMC Controller Interrupt System
MCBI
MMINT.7
MCBM EORI
MMINT.6 MMMSK.7
EORM EOCI
MMINT.5 MMMSK.6
EOCM EOFI
MMINT.4 MMMSK.5
EOFM F2FI
MMINT.3 MMMSK.4
MMC Interface Interrupt Request EMMC F2FM
IEN1.0 MMMSK.3
F1FI
MMINT.2
F1FM F2EI
MMINT.1 MMMSK.2
F2EM F1EI
MMINT.0 MMMSK.1
F1EM
MMMSK.0
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Registers
Table 112. MMCON0 Register MMCON0 (S:E4h) - MMC Control Register 0
7 DRPTR Bit Number 6 DTPTR 5 CRPTR 4 CTPTR 3 MBLOCK 2 DFMT 1 RFMT 0 CRCDIS
Bit Mnemonic Description Data Receive Pointer Reset Bit Set to reset the read pointer of the data FIFO. Clear to release the read pointer of the data FIFO. Data Transmit Pointer Reset Bit Set to reset the write pointer of the data FIFO. Clear to release the write pointer of the data FIFO. Command Receive Pointer Reset Bit Set to reset the read pointer of the receive command FIFO. Clear to release the read pointer of the receive command FIFO. Command Transmit Pointer Reset Bit Set to reset the write pointer of the transmit command FIFO. Clear to release the read pointer of the transmit command FIFO. Multi-block Enable Bit Set to select multi-block data format. Clear to select single block data format. Data Format Bit Set to select the block-oriented data format. Clear to select the stream data format. Response Format Bit Set to select the 48-bit response format. Clear to select the 136-bit response format. CRC7 Disable Bit Set to disable the CRC7 computation when receiving a response. Clear to enable the CRC7 computation when receiving a response.
7
DRPTR
6
DTPTR
5
CRPTR
4
CTPTR
3
MBLOCK
2
DFMT
1
RFMT
0
CRCDIS
Reset Value = 0000 0000b
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Table 113. MMCON1 Register MMCON1 (S:E5h) - MMC Control Register 1
7 BLEN3 Bit Number 7-4 6 BLEN2 5 BLEN1 4 BLEN0 3 DATDIR 2 DATEN 1 RESPEN 0 CMDEN
Bit Mnemonic Description BLEN3:0 Block Length Bits Refer to Table 111 for bits description. Do not program value > 1011b Data Direction Bit Set to select data transfer from host to card (write mode). Clear to select data transfer from card to host (read mode). Data Transmission Enable Bit Set and clear to enable data transmission immediately or after response has been received. Response Enable Bit Set and clear to enable the reception of a response following a command transmission. Command Transmission Enable Bit Set and clear to enable transmission of the command FIFO to the card.
3
DATDIR
2
DATEN
1
RESPEN
0
CMDEN
Reset Value = 0000 0000b Table 114. MMCON2 Register MMCON2 (S:E6h) - MMC Control Register 2
7 MMCEN Bit Number 6 DCR 5 CCR 4 3 2 DATD1 1 DATD0 0 FLOWC
Bit Mnemonic Description MMC Clock Enable Bit Set to enable the MCLK clocks and activate the MMC controller. Clear to disable the MMC clocks and freeze the MMC controller. Data Controller Reset Bit Set and clear to reset the data line controller in case of transfer abort. Command Controller Reset Bit Set and clear to reset the command line controller in case of transfer abort. Reserved The value read from these bits is always 0. Do not set these bits. Data Transmission Delay Bits Used to delay the data transmission after a response from 3 MMC clock periods (all bits cleared) to 9 MMC clock periods (all bits set) by step of 2 MMC clock periods. MMC Flow Control Bit Set to enable the flow control during data transfers. Clear to disable the flow control during data transfers.
7
MMCEN
6
DCR
5
CCR
4-3
-
2-1
DATD1:0
0
FLOWC
Reset Value = 0000 0000b
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Table 115. MMSTA Register MMSTA (S:DEh Read Only) - MMC Control and Status Register
7 Bit Number 7-6 6 5 CBUSY 4 CRC16S 3 DATFS 2 CRC7S 1 RESPFS 0 CFLCK
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Card Busy Flag Set by hardware when the card sends a busy state on the data line. Cleared by hardware when the card no more sends a busy state on the data line. CRC16 Status Bit Transmission mode Set by hardware when the token response reports a good CRC. Cleared by hardware when the token response reports a bad CRC. Reception mode Set by hardware when the CRC16 received in the data block is correct. Cleared by hardware when the CRC16 received in the data block is not correct. Data Format Status Bit Transmission mode Set by hardware when the format of the token response is correct. Cleared by hardware when the format of the token response is not correct. Reception mode Set by hardware when the format of the frame is correct. Cleared by hardware when the format of the frame is not correct. CRC7 Status Bit Set by hardware when the CRC7 computed in the response is correct. Cleared by hardware when the CRC7 computed in the response is not correct. This bit is not relevant when CRCDIS is set. Response Format Status Bit Set by hardware when the format of a response is correct. Cleared by hardware when the format of a response is not correct. Command FIFO Lock Bit Set by hardware to signal user not to write in the transmit command FIFO: busy state. Cleared by hardware to signal user the transmit command FIFO is available: idle state.
5
CBUSY
4
CRC16S
3
DATFS
2
CRC7S
1
RESPFS
0
CFLCK
Reset Value = 0000 0000b
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Table 116. MMINT Register MMINT (S:E7h Read Only) - MMC Interrupt Register
7 MCBI Bit Number 6 EORI 5 EOCI 4 EOFI 3 F2FI 2 F1FI 1 F2EI 0 F1EI
Bit Mnemonic Description MMC Card Busy Interrupt Flag Set by hardware when the card enters or exits its busy state (when the busy signal is asserted or deasserted on the data line). Cleared when reading MMINT. End of Response Interrupt Flag Set by hardware at the end of response reception. Cleared when reading MMINT. End of Command Interrupt Flag Set by hardware at the end of command transmission. Clear when reading MMINT. End of Frame Interrupt Flag Set by hardware at the end of frame (stream or block) transfer. Clear when reading MMINT. FIFO 2 Full Interrupt Flag Set by hardware when second FIFO becomes full. Cleared by hardware when second FIFO becomes empty. FIFO 1 Full Interrupt Flag Set by hardware when first FIFO becomes full. Cleared by hardware when first FIFO becomes empty. FIFO 2 Empty Interrupt Flag Set by hardware when second FIFO becomes empty. Cleared by hardware when second FIFO becomes full. FIFO 1 Empty Interrupt Flag Set by hardware when first FIFO becomes empty. Cleared by hardware when first FIFO becomes full.
7
MCBI
6
EORI
5
EOCI
4
EOFI
3
F2FI
2
F1FI
1
F2EI
0
F1EI
Reset Value = 0000 0011b
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Table 117. MMMSK Register MMMSK (S:DFh) - MMC Interrupt Mask Register
7 MCBM Bit Number 6 EORM 5 EOCM 4 EOFM 3 F2FM 2 F1FM 1 F2EM 0 F1EM
Bit Mnemonic Description MMC Card Busy Interrupt Mask Bit Set to prevent MCBI flag from generating an MMC interrupt. Clear to allow MCBI flag to generate an MMC interrupt. End Of Response Interrupt Mask Bit Set to prevent EORI flag from generating an MMC interrupt. Clear to allow EORI flag to generate an MMC interrupt. End Of Command Interrupt Mask Bit Set to prevent EOCI flag from generating an MMC interrupt. Clear to allow EOCI flag to generate an MMC interrupt. End Of Frame Interrupt Mask Bit Set to prevent EOFI flag from generating an MMC interrupt. Clear to allow EOFI flag to generate an MMC interrupt. FIFO 2 Full Interrupt Mask Bit Set to prevent F2FI flag from generating an MMC interrupt. Clear to allow F2FI flag to generate an MMC interrupt. FIFO 1 Full Interrupt Mask Bit Set to prevent F1FI flag from generating an MMC interrupt. Clear to allow F1FI flag to generate an MMC interrupt. FIFO 2 Empty Interrupt Mask Bit Set to prevent F2EI flag from generating an MMC interrupt. Clear to allow F2EI flag to generate an MMC interrupt. FIFO 1 Empty Interrupt Mask Bit Set to prevent F1EI flag from generating an MMC interrupt. Clear to allow F1EI flag to generate an MMC interrupt.
7
MCBM
6
EORM
5
EOCM
4
EOFM
3
F2FM
2
F1FM
1
F2EM
0
F1EM
Reset Value = 1111 1111b Table 118. MMCMD Register MMCMD (S:DDh) - MMC Command Register
7 MC7 Bit Number 6 MC6 5 MC5 4 MC4 3 MC3 2 MC2 1 MC1 0 MC0
Bit Mnemonic Description MMC Command Receive Byte Output (read) register of the response FIFO. MMC Command Transmit Byte Input (write) register of the command FIFO.
7-0
MC7:0
Reset Value = 1111 1111b
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Table 119. MMDAT Register MMDAT (S:DCh) - MMC Data Register
7 MD7 Bit Number 7-0 6 MD6 5 MD5 4 MD4 3 MD3 2 MD2 1 MD1 0 MD0
Bit Mnemonic Description MD7:0 MMC Data Byte Input (write) or output (read) register of the data FIFO.
Reset Value = 1111 1111b Table 120. MMCLK Register MMCLK (S:EDh) - MMC Clock Divider Register
7 MMCD7 Bit Number 7-0 6 MMCD6 5 MMCD5 4 MMCD4 3 MMCD3 2 MMCD2 1 MMCD1 0 MMCD0
Bit Mnemonic Description MMCD7:0 MMC Clock Divider 8-bit divider for MMC clock generation.
Reset Value = 0000 0000b
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IDE/ATAPI Interface
The AT8xC51SND1C provides an IDE/ATAPI interface allowing connection of devices such as CD-ROM reader, CompactFlash cards, Hard Disk Drive, etc. It consists of a 16bit data transfer (read or write) between the AT8xC51SND1C and the IDE device. The IDE interface mode is enabled by setting the EXT16 bit in AUXR (see Figure 29, page 29). As soon as this bit is set, all MOVX instructions read or write are done in a 16bit mode compare to the standard 8-bit mode. P0 carries the low order multiplexed address and data bus (A7:0, D7:0) while P2 carries the high order multiplexed address and data bus (A15:8, D15:8). When writing data in IDE mode, the ACC contains D7:0 data (as in 8-bit mode) while DAT16H register (see Table 122) contains D15:8 data. When reading data in IDE mode, D7:0 data is returned in ACC while D15:8 data is returned in DAT16H. Figure 90 shows the IDE read bus cycle while Figure 91 shows the IDE write bus cycle. For simplicity, these figures depict the bus cycle waveforms in idealized form and do not provide precise timing information. For IDE bus cycle timing parameters refer to the Section "AC Characteristics". IDE cycle takes 6 CPU clock periods which is equivalent to 12 oscillator clock periods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode, refer to the Section "X2 Feature", page 12. Slow IDE devices can be accessed by stretching the read and write cycles. This is done using the M0 bit in AUXR. Setting this bit changes the width of the RD and WR signals from 3 to 15 CPU clock periods. Figure 90. IDE Read Waveforms
CPU Clock ALE
Description
RD(1)
P0 P2
P2 DPL or Ri DPH or P2(2),(3) D7:0
D15:8
P2
Notes:
1. RD signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. 3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH.
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Figure 91. IDE Write Waveforms
CPU Clock ALE
WR(1)
P0 P2
P2 DPL or Ri DPH or P2(2),(3) D7:0
D15:8
P2
Notes:
1. WR signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. 3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH.
IDE Device Connection
Figure 92 and Figure 93 show 2 examples on how to interface up to 2 IDE devices to the AT8xC51SND1C. In both examples P0 carries IDE low order data bits D7:0, P2 carries IDE high order data bits D15:8, while RD and WR signals are respectively connected to the IDE nIOR and nIOW signals. Other IDE control signals are generated by the external address latch outputs in the first example while they are generated by some port I/Os in the second one. Using an external latch will achieve higher transfer rate. Figure 92. IDE Device Connection Example 1
AT8xC51SND1C P2 IDE Device 0 D15-8 D7:0 P0 ALE Px.y RD WR A2:0 Latch nCS1:0 nRESET nIOR nIOW IDE Device 1 D15-8 D7:0 A2:0 nCS1:0 nRESET nIOR nIOW
Figure 93. IDE Device Connection Example 2
AT8xC51SND1C P2/A15:8 P0/AD7:0 P4.2:0 P4.4:3 P4.5 RD WR IDE Device 0 D15-8 D7:0 A2:0 nCS1:0 nRESET nIOR nIOW IDE Device 1 D15-8 D7:0 A2:0 nCS1:0 nRESET nIOR nIOW
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Table 121. External Data Memory Interface Signals
Signal Name Type Description Address Lines Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. Address/Data Lines Multiplexed lower address and data lines for the IDE interface. Address Latch Enable ALE signals indicates that valid address information is available on lines AD7:0. Read Read signal output to external data memory. Write Write signal output to external memory. Alternate Function
A15:8
I/O
P2.7:0
AD7:0
I/O
P0.7:0
ALE
O
-
RD
O
P3.7
WR
O
P3.6
Registers
Table 122. DAT16H Register DAT16H (S:F9h) - Data 16 High Order Byte
7 D15 Bit Number 6 D14 5 D13 4 D12 3 D11 2 D10 1 D9 0 D8
Bit Mnemonic Description Data 16 High Order Byte When EXT16 bit is set, DAT16H is set by software with the high order data Byte prior any MOVX write instruction. When EXT16 bit is set, DAT16H contains the high order data Byte after any MOVX read instruction.
7-0
D15:8
Reset Value =XXXX XXXXb
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Serial I/O Port
The serial I/O port in the AT8xC51SND1C provides both synchronous and asynchronous communication modes. It operates as a Synchronous Receiver and Transmitter in one single mode (Mode 0) and operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous modes support framing error detection and multiprocessor communication with automatic address recognition. SM0 and SM1 bits in SCON register (see Figure 125) are used to select a mode among the single synchronous and the three asynchronous modes according to Table 123. Table 123. Serial I/O Port Mode Selection
SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Description Synchronous Shift Register 8-bit UART 9-bit UART 9-bit UART Baud Rate Fixed/Variable Variable Fixed Variable
Mode Selection
Baud Rate Generator
Depending on the mode and the source selection, the baud rate can be generated from either the Timer 1 or the Internal Baud Rate Generator. The Timer 1 can be used in Modes 1 and 3 while the Internal Baud Rate Generator can be used in Modes 0, 1 and 3. The addition of the Internal Baud Rate Generator allows freeing of the Timer 1 for other purposes in the application. It is highly recommended to use the Internal Baud Rate Generator as it allows higher and more accurate baud rates than Timer 1. Baud rate formulas depend on the modes selected and are given in the following mode sections.
Timer 1
When using Timer 1, the Baud Rate is derived from the overflow of the timer. As shown in Figure 94 Timer 1 is used in its 8-bit auto-reload mode (detailed in Section "Mode 2 (8-bit Timer with Auto-Reload)", page 53). SMOD1 bit in PCON register allows doubling of the generated baud rate. Figure 94. Timer 1 Baud Rate Generator Block Diagram
PER CLOCK /6 0 1
TL1 (8 bits)
Overflow
/2
0 1
T1 C/T1#
TMOD.6
To serial Port
INT1
GATE1
TMOD.7
SMOD1
PCON.7
TH1 (8 bits)
T1 CLOCK
TR1
TCON.6
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Internal Baud Rate Generator When using the Internal Baud Rate Generator, the Baud Rate is derived from the overflow of the timer. As shown in Figure 95 the Internal Baud Rate Generator is an 8-bit auto-reload timer fed by the peripheral clock or by the peripheral clock divided by 6 depending on the SPD bit in BDRCON register (see Table 129). The Internal Baud Rate Generator is enabled by setting BBR bit in BDRCON register. SMOD1 bit in PCON register allows doubling of the generated baud rate. Figure 95. Internal Baud Rate Generator Block Diagram
PER CLOCK /6 0 1
BRG (8 bits) BRR
BDRCON.4
Overflow
/2
0 1
To serial Port
SPD
BDRCON.1
SMOD1
PCON.7
BRL (8 bits)
IBRG CLOCK
Synchronous Mode (Mode 0)
Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0 capabilities of a device with shift registers. The transmit data (TXD) pin outputs a set of eight clock pulses while the receive data (RXD) pin transmits or receives a Byte of data. The 8-bit data are transmitted and received least-significant bit (LSB) first. Shifts occur at a fixed Baud Rate (see Section "Baud Rate Selection (Mode 0)", page 136). Figure 96 shows the serial port block diagram in Mode 0. Figure 96. Serial I/O Port Block Diagram (Mode 0)
SCON.6 SCON.7
SM1
SM0 SBUF Tx SR RXD
Mode Decoder
M3 M2 M1 M0
SBUF Rx SR Mode Controller
PER CLOCK
TI
SCON.1
RI
SCON.0
BRG CLOCK
Baud Rate Controller
TXD
Transmission (Mode 0)
To start a transmission mode 0, write to SCON register clearing bits SM0, SM1. As shown in Figure 97, writing the Byte to transmit to SBUF register starts the transmission. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle composed of a high level then low level signal on TXD. During the eighth clock cycle the MSB (D7) is on the RXD pin. Then, hardware drives the RXD pin high and asserts TI to indicate the end of the transmission.
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Figure 97. Transmission Waveforms (Mode 0)
TXD Write to SBUF RXD TI
D0 D1 D2 D3 D4 D5 D6 D7
Reception (Mode 0)
To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits and setting the REN bit. As shown in Figure 98, Clock is pulsed and the LSB (D0) is sampled on the RXD pin. The D0 bit is then shifted into the shift register. After eight samplings, the MSB (D7) is shifted into the shift register, and hardware asserts RI bit to indicate a completed reception. Software can then read the received Byte from SBUF register. Figure 98. Reception Waveforms (Mode 0)
TXD Write to SCON RXD RI
Set REN, Clear RI D0 D1 D2 D3 D4 D5 D6 D7
Baud Rate Selection (Mode 0)
In mode 0, the baud rate can be either, fixed or variable. As shown in Figure 99, the selection is done using M0SRC bit in BDRCON register. Figure 100 gives the baud rate calculation formulas for each baud rate source. Figure 99. Baud Rate Source Selection (mode 0)
PER CLOCK IBRG CLOCK /6 0
To Serial Port
1
M0SRC
BDRCON.0
Figure 100. Baud Rate Formulas (Mode 0)
Baud_Rate= Baud_Rate= FPER 6 2SMOD1 FPER 6(1-SPD) 32 (256 -BRL) 2SMOD1 FPER 32 Baud_Rate
BRL= 256 -
6
(1-SPD)
a. Fixed Formula
b. Variable Formula
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Asynchronous Modes (Modes 1, 2 and 3)
The Serial Port has one 8-bit and 2 9-bit asynchronous modes of operation. Figure 101 shows the Serial Port block diagram in such asynchronous modes. Figure 101. Serial I/O Port Block Diagram (Modes 1, 2 and 3)
SCON.6 SCON.7 SCON.3
SM1
SM0
TB8 SBUF Tx SR TXD
Mode Decoder
M3 M2 M1 M0 T1 CLOCK IBRG CLOCK PER CLOCK
Rx SR Mode & Clock Controller SBUF Rx SM2
SCON.4
RXD
RB8
SCON.2
TI
SCON.1
RI
SCON.0
Mode 1
Mode 1 is a full-duplex, asynchronous mode. The data frame (see Figure 102) consists of 10 bits: one start, eight data bits and one stop bit. Serial data is transmitted on the TXD pin and received on the RXD pin. When a data is received, the stop bit is read in the RB8 bit in SCON register. Figure 102. Data Frame Format (Mode 1)
Mode 1
Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit
8-bit data
Modes 2 and 3
Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 103) consists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin and received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON register. On transmit, the ninth data bit is written to TB8 bit in SCON register. Alternatively, you can use the ninth bit can be used as a command/data flag. Figure 103. Data Frame Format (Modes 2 and 3)
D0 Start bit D1 D2 D3 D4 9-bit data D5 D6 D7 D8 Stop bit
Transmission (Modes 1, 2 and 3)
To initiate a transmission, write to SCON register, set the SM0 and SM1 bits according to Table 123, and set the ninth bit by writing to TB8 bit. Then, writing the Byte to be transmitted to SBUF register starts the transmission. To prepare for reception, write to SCON register, set the SM0 and SM1 bits according to Table 123, and set the REN bit. The actual reception is then initiated by a detected highto-low transition on the RXD pin.
Reception (Modes 1, 2 and 3)
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Framing Error Detection (Modes 1, 2 and 3)
Framing error detection is provided for the three asynchronous modes. To enable the framing bit error detection feature, set SMOD0 bit in PCON register as shown in Figure 104. When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by 2 devices. If a valid stop bit is not found, the software sets FE bit in SCON register. Software may examine FE bit after each reception to check for data errors. Once set, only software or a chip reset clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on stop bit instead of the last data bit as detailed in Figure 110. Figure 104. Framing Error Block Diagram
Framing Error Controller
FE 1
SM0/FE
0
SCON.7
SM0 SMOD0
PCON.6
Baud Rate Selection (Modes 1 and 3)
In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud Rate Generator and allows different baud rate in reception and transmission. As shown in Figure 105 the selection is done using RBCK and TBCK bits in BDRCON register. Figure 106 gives the baud rate calculation formulas for each baud rate source while Table 124 details Internal Baud Rate Generator configuration for different peripheral clock frequencies and giving baud rates closer to the standard baud rates. Figure 105. Baud Rate Source Selection (Modes 1 and 3)
T1 CLOCK IBRG CLOCK T1 CLOCK IBRG CLOCK
0 1
/ 16
To Serial Rx Port
0 1
/ 16
To Serial Tx Port
RBCK
BDRCON.2
TBCK
BDRCON.3
Figure 106. Baud Rate Formulas (Modes 1 and 3)
Baud_Rate= 6
(1-SPD)
2SMOD1 FPER 32 (256 -BRL) 2SMOD1 FPER 32 Baud_Rate
Baud_Rate=
2SMOD1 FPER 6 32 (256 -TH1) 2SMOD1 FPER 192 Baud_Rate
BRL= 256 -
6
(1-SPD)
TH1= 256 -
a. IBRG Formula
b. T1 Formula
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Table 124. Internal Baud Rate Generator Value
FPER = 6 MHz(1) Baud Rate 115200 57600 38400 19200 9600 4800 SPD 1 1 1 1 SMOD1 1 1 1 1 BRL 246 236 217 178 Error % 2.34 2.34 0.16 0.16 SPD 1 1 1 1 1 FPER = 8 MHz(1) SMOD1 1 1 1 1 1 BRL 247 243 230 204 152 Error % 3.55 0.16 0.16 0.16 0.16 SPD 1 1 1 1 1 FPER = 10 MHz(1) SMOD1 1 1 1 1 1 BRL 245 240 223 191 126 Error % 1.36 1.73 1.36 0.16 0.16
FPER = 12 MHz(2) Baud Rate 115200 57600 38400 19200 9600 4800 SPD 1 1 1 1 1 SMOD1 1 1 1 1 1 BRL 243 236 217 178 100 Error % 0.16 2.34 0.16 0.16 0.16 SPD 1 1 1 1 1 1
FPER = 16 MHz(2) SMOD1 1 1 1 1 1 1 BRL 247 239 230 204 152 48 Error % 3.55 2.12 0.16 0.16 0.16 0.16 SPD 1 1 1 1 1 1
FPER = 20 MHz(2) SMOD1 1 1 1 1 1 0 BRL 245 234 223 191 126 126 Error % 1.36 1.36 1.36 0.16 0.16 0.16
Notes:
1. These frequencies are achieved in X1 mode, FPER = FOSC / 2. 2. These frequencies are achieved in X2 mode, FPER = FOSC.
Baud Rate Selection (Mode 2)
In mode 2, the baud rate can only be programmed to 2 fixed values: 1/16 or 1/32 of the peripheral clock frequency. As shown in Figure 107 the selection is done using SMOD1 bit in PCON register. Figure 108 gives the baud rate calculation formula depending on the selection. Figure 107. Baud Rate Generator Selection (Mode 2)
PER CLOCK
/2
0 1
/ 16
To Serial Port
SMOD1
PCON.7
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Figure 108. Baud Rate Formula (Mode 2)
Baud_Rate= 2SMOD1 FPER 32
Multiprocessor Communication (Modes 2 and 3)
Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To enable this feature, set SM2 bit in SCON register. When the multiprocessor communication feature is enabled, the serial Port can differentiate between data frames (ninth bit clear) and address frames (ninth bit set). This allows the AT8xC51SND1C to function as a slave processor in an environment where multiple slave processors share a single serial line. When the multiprocessor communication feature is enabled, the receiver ignores frames with the ninth bit clear. The receiver examines frames with the ninth bit set for an address match. If the received address matches the slaves address, the receiver hardware sets RB8 and RI bits in SCON register, generating an interrupt. The addressed slave's software then clears SM2 bit in SCON register and prepares to receive the data Bytes. The other slaves are unaffected by these data Bytes because they are waiting to respond to their own addresses.
Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the Serial Port to examine the address of each incoming command frame. Only when the Serial Port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, the automatic address recognition feature in mode 1 may be enabled. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device's address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e, setting SM2 bit in SCON register in mode 0 has no effect).
Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register is a mask Byte that contains don't care bits (defined by zeros) to form the device's given address. The don't care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask Byte must be 1111 1111b. For example:
SADDR = 0101 0110b SADEN = 1111 1100b Given = 0101 01XXb
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The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR = 1111 0001b SADEN = 1111 1010b Given = 1111 0X0Xb Slave B:SADDR = 1111 0011b SADEN = 1111 1001b Given = 1111 0XX1b Slave C:SADDR = 1111 0010b SADEN = 1111 1101b Given = 1111 00X1b
The SADEN Byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don't-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000B). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don't care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011B). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001B). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don't-care bits, e.g.:
SADDR = 0101 0110b SADEN = 1111 1100b (SADDR | SADEN)=1111 111Xb
The use of don't-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR = 1111 0001b SADEN = 1111 1010b Given = 1111 1X11b, Slave B:SADDR = 1111 0011b SADEN = 1111 1001b Given = 1111 1X11b, Slave C:SADDR = 1111 0010b SADEN = 1111 1101b Given = 1111 1111b,
For slaves A and B, bit 2 is a don't care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send the address FFh. To communicate with slaves A and B, but not slave C, the master must send the address FBh. Reset Address On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don't care bits). This ensures that the Serial Port is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition.
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Interrupt
The Serial I/O Port handles 2 interrupt sources that are the "end of reception" (RI in SCON) and "end of transmission" (TI in SCON) flags. As shown in Figure 109 these flags are combined together to appear as a single interrupt source for the C51 core. Flags must be cleared by software when executing the serial interrupt service routine. The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register. Depending on the selected mode and weather the framing error detection is enabled or disabled, RI flag is set during the stop bit or during the ninth bit as detailed in Figure 110. Figure 109. Serial I/O Interrupt System
SCON.0 RI Serial I/O Interrupt Request TI SCON.1 ES IEN0.4
Figure 110. Interrupt Waveforms
a. Mode 1 RXD Start Bit RI SMOD0 = X FE SMOD0 = 1 b. Mode 2 and 3 RXD Start bit RI SMOD0 = 0 RI SMOD0 = 1 FE SMOD0 = 1 D0 D1 D2 D3 D4 9-bit data D5 D6 D7 D8 Stop bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit
8-bit Data
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Registers
Table 125. SCON Register SCON (S:98h) - Serial Control Register
7 FE/SM0 Bit Number 6 OVR/SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Bit Mnemonic Description Framing Error Bit To select this function, set SMOD0 bit in PCON register. Set by hardware to indicate an invalid stop bit. Must be cleared by software. Serial Port Mode Bit 0 Refer to Table 123 for mode selection. Serial Port Mode Bit 1 Refer to Table 123 for mode selection. Serial Port Mode Bit 2 Set to enable the multiprocessor communication and automatic address recognition features. Clear to disable the multiprocessor communication and automatic address recognition features. Receiver Enable Bit Set to enable reception. Clear to disable reception. Transmit Bit 8 Modes 0 and 1: Not used. Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8. Receiver Bit 8 Mode 0: Not used. Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit received. Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit received. Transmit Interrupt Flag Set by the transmitter after the last data bit is transmitted. Must be cleared by software. Receive Interrupt Flag Set by the receiver after the stop bit of a frame has been received. Must be cleared by software.
FE 7 SM0
6
SM1
5
SM2
4
REN
3
TB8
2
RB8
1
TI
0
RI
Reset Value = 0000 0000b
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Table 126. SBUF Register SBUF (S:99h) - Serial Buffer Register
7 SD7 Bit Number 6 SD6 5 SD5 4 SD4 3 SD3 2 SD2 1 SD1 0 SD0
Bit Mnemonic Description Serial Data Byte Read the last data received by the serial I/O Port. Write the data to be transmitted by the serial I/O Port.
7-0
SD7:0
Reset value = XXXX XXXXb Table 127. SADDR Register SADDR (S:A9h) - Slave Individual Address Register
7 SAD7 Bit Number 7-0 6 SAD6 5 SAD5 4 SAD4 3 SAD3 2 SAD2 1 SAD1 0 SAD0
Bit Mnemonic Description SAD7:0 Slave Individual Address
Reset Value = 0000 0000b Table 128. SADEN Register SADEN (S:B9h) - Slave Individual Address Mask Byte Register
7 SAE7 Bit Number 7-0 6 SAE6 5 SAE5 4 SAE4 3 SAE3 2 SAE2 1 SAE1 0 SAE0
Bit Mnemonic Description SAE7:0 Slave Address Mask Byte
Reset Value = 0000 0000b
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Table 129. BDRCON Register BDRCON (S:92h) - Baud Rate Generator Control Register
7 Bit Number 7-5 6 5 4 BRR 3 TBCK 2 RBCK 1 SPD 0 M0SRC
Bit Mnemonic Description Reserved The value read from these bits are indeterminate. Do not set these bits. Baud Rate Run Bit Set to enable the baud rate generator. Clear to disable the baud rate generator. Transmission Baud Rate Selection Bit Set to select the baud rate generator as transmission baud rate generator. Clear to select the Timer 1 as transmission baud rate generator. Reception Baud Rate Selection Bit Set to select the baud rate generator as reception baud rate generator. Clear to select the Timer 1 as reception baud rate generator. Baud Rate Speed Bit Set to select high speed baud rate generation. Clear to select low speed baud rate generation. Mode 0 Baud Rate Source Bit Set to select the variable baud rate generator in Mode 0. Clear to select fixed baud rate in Mode 0.
4
BRR
3
TBCK
2
RBCK
1
SPD
0
M0SRC
Reset Value = XXX0 0000b Table 130. BRL Register BRL (S:91h) - Baud Rate Generator Reload Register
7 BRL7 Bit Number 7-0 6 BRL6 5 BRL5 4 BRL4 3 BRL3 2 BRL2 1 BRL1 0 BRL0
Bit Mnemonic Description BRL7:0 Baud Rate Reload Value
Reset Value = 0000 0000b
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Synchronous Peripheral Interface
The AT8xC51SND1C implements a Synchronous Peripheral Interface with master and slave modes capability. Figure 111 shows an SPI bus configuration using the AT8xC51SND1C as master connected to slave peripherals while Figure 112 shows an SPI bus configuration using the AT8xC51SND1C as slave of an other master. The bus is made of three wires connecting all the devices together: * Master Output Slave Input (MOSI): it is used to transfer data in series from the master to a slave. It is driven by the master. Master Input Slave Output (MISO): it is used to transfer data in series from a slave to the master. It is driven by the selected slave. Serial Clock (SCK): it is used to synchronize the data transmission both in and out the devices through their MOSI and MISO lines. It is driven by the master for eight clock cycles which allows to exchange one Byte on the serial lines.
*
*
Each slave peripheral is selected by one Slave Select pin (SS). If there is only one slave, it may be continuously selected with SS tied to a low level. Otherwise, the AT8xC51SND1C may select each device by software through port pins (Pn.x). Special care should be taken not to select 2 slaves at the same time to avoid bus conflicts. Figure 111. Typical Master SPI Bus Configuration
Pn.z Pn.y Pn.x SS SO
DataFlash 1
SI SCK
SS DataFlash 2 SO SI SCK
SS SO
LCD Controller
SI SCK
AT8xC51SND1C
P4.0 P4.1 P4.2
MISO MOSI SCK
Figure 112. Typical Slave SPI Bus Configuration
SSn SS1 SS0 SS SO SS
Slave 1
SI SCK
SS SO
Slave 2
SI SCK
AT8xC51SND1C Slave n
MISO MOSI SCK
MASTER
MISO MOSI SCK
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Description
The SPI controller interfaces with the C51 core through three special function registers: SPCON, the SPI control register (see Table 132); SPSTA, the SPI status register (see Table 133); and SPDAT, the SPI data register (see Table 134). The SPI operates in master mode when the MSTR bit in SPCON is set. Figure 113 shows the SPI block diagram in master mode. Only a master SPI module can initiate transmissions. Software begins the transmission by writing to SPDAT. Writing to SPDAT writes to the shift register while reading SPDAT reads an intermediate register updated at the end of each transfer. The Byte begins shifting out on the MOSI pin under the control of the bit rate generator. This generator also controls the shift register of the slave peripheral through the SCK output pin. As the Byte shifts out, another Byte shifts in from the slave peripheral on the MISO pin. The Byte is transmitted most significant bit (MSB) first. The end of transfer is signaled by SPIF being set. When the AT8xC51SND1C is the only master on the bus, it can be useful not to use SS# pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. Figure 113. SPI Master Mode Block Diagram
MOSI/P4.1
Master Mode
MISO/P4.0
I
8-bit Shift Register
SPDAT WR
Q Internal Bus
SCK/P4.2 SPDAT RD SS#/P4.3 MODF SSDIS
SPCON.5 SPSTA.4
Control and Clock Logic
WCOL
SPSTA.6
PER CLOCK
Bit Rate Generator SPEN
SPCON.6
SPIF
SPSTA.7
SPR2:0
SPCON
CPHA
SPCON.2
CPOL
SPCON.3
Note:
MSTR bit in SPCON is set to select master mode.
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Slave Mode
The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has been loaded in SPDAT. Figure 114 shows the SPI block diagram in slave mode. In slave mode, before a data transmission occurs, the SS pin of the slave SPI must be asserted to low level. SS must remain low until the transmission of the Byte is complete. In the slave SPI module, data enters the shift register through the MOSI pin under the control of the serial clock provided by the master SPI module on the SCK input pin. When the master starts a transmission, the data in the shift register begins shifting out on the MISO pin. The end of transfer is signaled by SPIF being set. When the AT8xC51SND1C is the only slave on the bus, it can be useful not to use SS# pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. This bit has no effect when CPHA is cleared (see Section "SS Management", page 150).
Figure 114. SPI Slave Mode Block Diagram
MISO/P4.2
MOSI/P4.1
I
8-bit Shift Register
SPDAT WR
Q Internal Bus
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SCK/P4.2 Control and Clock Logic SS/P4.3 SSDIS
SPCON.5
SPDAT RD SPIF
SPSTA.7
CPHA
SPCON.2
CPOL
SPCON.3
Note:
1. MSTR bit in SPCON is cleared to select slave mode.
Bit Rate
The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and SPR0 control bits in SPCON according to Table 131. These bit rates are derived from the peripheral clock (FPER) issued from the Clock Controller block as detailed in Section "Oscillator", page 12.
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Table 131. Serial Bit Rates
Bit Rate (kHz) Vs FPER SPR2 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 6 MHz(1) 8 MHz(1) 10 MHz(1) 12 MHz(2) 16 MHz(2) 20 MHz(2) 3000 1500 750 375 187.5 93.75 46.875 6000 4000 2000 1000 500 250 125 62.5 8000 5000 2500 1250 625 312.5 156.25 78.125 10000 6000 3000 1500 750 375 187.5 93.75 12000 8000 4000 2000 1000 500 250 125 16000 10000 5000 2500 1250 625 312.5 156.25 20000 FPER Divider 2 4 8 16 32 64 128 1
Notes:
1. These frequencies are achieved in X1 mode, FPER = FOSC / 2. 2. These frequencies are achieved in X2 mode, FPER = FOSC.
Data Transfer
The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle state(1) while the Clock Phase bit (CPHA in SPCON) defines the edges on which the input data are sampled and the edges on which the output data are shifted (see Figure 115 and Figure 116). The SI signal is output from the selected slave and the SO signal is the output from the master. The AT8xC51SND1C captures data from the SI line while the selected slave captures data from the SO line. For simplicity, Figure 115 and Figure 116 depict the SPI waveforms in idealized form and do not provide precise timing information. For timing parameters refer to the Section "AC Characteristics".
Note: 1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.
Figure 115. Data Transmission Format (CPHA = 0)
SCK Cycle Number SPEN (Internal) 1 2 3 4 5 6 7 8
SCK (CPOL = 0) SCK (CPOL = 1)
MOSI (From Master)
MSB
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
MISO (From Slave)
MSB
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
SS (to slave) Capture point
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Figure 116. Data Transmission Format (CPHA = 1)
SCK cycle number SPEN (internal) 1 2 3 4 5 6 7 8
SCK (CPOL = 0) SCK (CPOL = 1)
MOSI (from master)
MSB
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
MISO (from slave)
MSB
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
SS (to slave) Capture point
SS Management
Figure 115 shows an SPI transmission with CPHA = 0, where the first SCK edge is the MSB capture point. Therefore the slave starts to output its MSB as soon as it is selected: SS asserted to low level. SS must then be deasserted between each Byte transmission (see Figure 117). SPDAT must be loaded with a data before SS is asserted again. Figure 116 shows an SPI transmission with CPHA = 1, where the first SCK edge is used by the slave as a start of transmission signal. Therefore, SS may remain asserted between each Byte transmission (see Figure 117). Figure 117. SS Timing Diagram
SI/SO SS (CPHA = 0) SS (CPHA = 1) Byte 1 Byte 2 Byte 3
Error Conditions
The following flags signal the SPI error conditions: * MODF in SPSTA signals a mode fault. MODF flag is relevant only in master mode when SS usage is enabled (SSDIS bit cleared). It signals when set that an other master on the bus has asserted SS pin and so, may create a conflict on the bus with 2 master sending data at the same time. A mode fault automatically disables the SPI (SPEN cleared) and configures the SPI in slave mode (MSTR cleared). MODF flag can trigger an interrupt as explained in Section "Interrupt", page 151. MODF flag is cleared by reading SPSTA and re-configuring SPI by writing to SPCON. WCOL in SPSTA signals a write collision. WCOL flag is set when SPDAT is loaded while a transfer is on-going. In this case data is not written to SPDAT and transfer continue uninterrupted. WCOL flag does not trigger any interrupt and is relevant jointly with SPIF flag. WCOL flag is cleared after reading SPSTA and writing new data to SPDAT while no transfer is on-going.
*
*
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Interrupt
The SPI handles 2 interrupt sources that are the "end of transfer" and the "mode fault" flags. As shown in Figure 118, these flags are combined toghether to appear as a single interrupt source for the C51 core. The SPIF flag is set at the end of an 8-bit shift in and out and is cleared by reading SPSTA and then reading from or writing to SPDAT. The MODF flag is set in case of mode fault error and is cleared by reading SPSTA and then writing to SPCON. The SPI interrupt is enabled by setting ESPI bit in IEN1 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register. Figure 118. SPI Interrupt System
SPIF
SPSTA.7
MODF
SPSTA.4
SPI Controller Interrupt Request ESPI
IEN1.2
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Configuration
Master Configuration Slave Configuration
The SPI configuration is made through SPCON. The SPI operates in master mode when the MSTR bit in SPCON is set. The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has been loaded is SPDAT. There are 2 possible methods to exchange data in master and slave modes: * * polling interrupts
Data Exchange
Master Mode with Polling Policy
Figure 119 shows the initialization phase and the transfer phase flows using the polling method. Using this flow prevents any overrun error occurrence. The bit rate is selected according to Table 131. The transfer format depends on the slave peripheral. SS may be deasserted between transfers depending also on the slave peripheral. SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the "end of transfer" check). This polling method provides the fastest effective transmission and is well adapted when communicating at high speed with other microcontrollers. However, the procedure may then be interrupted at any time by higher priority tasks. Figure 119. Master SPI Polling Flows
SPI Initialization Polling Policy SPI Transfer Polling Policy
Disable interrupt SPIE = 0
Select Slave Pn.x = L
Select Master Mode MSTR = 1
Start Transfer write data in SPDAT
Select Bit Rate program SPR2:0
End Of Transfer? SPIF = 1?
Select Format program CPOL & CPHA Get Data Received read SPDAT Enable SPI SPEN = 1 Last Transfer?
Deselect Slave Pn.x = H
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Master Mode with Interrupt Figure 120 shows the initialization phase and the transfer phase flows using the interrupt. Using this flow prevents any overrun error occurrence. The bit rate is selected according to Table 131. The transfer format depends on the slave peripheral. SS may be deasserted between transfers depending also on the slave peripheral. Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag. Clear is effective when reading SPDAT. Figure 120. Master SPI Interrupt Flows
SPI Initialization Interrupt Policy SPI Interrupt Service Routine
Select Master Mode MSTR = 1
Read Status Read SPSTA
Select Bit Rate program SPR2:0
Get Data Received read SPDAT
Select Format program CPOL & CPHA
Start New Transfer write data in SPDAT
Enable interrupt ESPI =1
Last Transfer?
Enable SPI SPEN = 1 Deselect Slave Pn.x = H Select Slave Pn.x = L Disable interrupt SPIE = 0 Start Transfer write data in SPDAT
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Slave Mode with Polling Policy
Figure 121 shows the initialization phase and the transfer phase flows using the polling. The transfer format depends on the master controller. SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the "end of reception" check). This provides the fastest effective transmission and is well adapted when communicating at high speed with other Microcontrollers. However, the process may then be interrupted at any time by higher priority tasks. Figure 121. Slave SPI Polling Flows
SPI Initialization Polling Policy SPI Transfer Polling Policy
Disable interrupt SPIE = 0
Data Received? SPIF = 1?
Select Slave Mode MSTR = 0 Get Data Received read SPDAT Select Format program CPOL & CPHA Prepare Next Transfer write data in SPDAT Enable SPI SPEN = 1
Prepare Transfer write data in SPDAT
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Slave Mode with Interrupt Policy Figure 120 shows the initialization phase and the transfer phase flows using the interrupt. The transfer format depends on the master controller. Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag. Clear is effective when reading SPDAT. Figure 122. Slave SPI Interrupt Policy Flows
SPI Initialization Interrupt Policy SPI Interrupt Service Routine
Select Slave Mode MSTR = 0
Get Status Read SPSTA
Select Format program CPOL & CPHA
Get Data Received read SPDAT
Enable interrupt ESPI =1
Prepare New Transfer write data in SPDAT
Enable SPI SPEN = 1
Prepare Transfer write data in SPDAT
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Registers
Table 132. SPCON Register SPCON (S:C3h) - SPI Control Register
7 SPR2 Bit Number 7 6 SPEN 5 SSDIS 4 MSTR 3 CPOL 2 CPHA 1 SPR1 0 SPR0
Bit Mnemonic Description SPR2 SPI Rate Bit 2 Refer to Table 131 for bit rate description. SPI Enable Bit Set to enable the SPI interface. Clear to disable the SPI interface. Slave Select Input Disable Bit Set to disable SS in both master and slave modes. In slave mode this bit has no effect if CPHA = 0. Clear to enable SS in both master and slave modes. Master Mode Select Set to select the master mode. Clear to select the slave mode. SPI Clock Polarity Bit(1)
6
SPEN
5
SSDIS
4
MSTR
3
CPOL
Set to have the clock output set to high level in idle state. Clear to have the clock output set to low level in idle state. SPI Clock Phase Bit Set to have the data sampled when the clock returns to idle state (see CPOL). Clear to have the data sampled when the clock leaves the idle state (see CPOL). SPI Rate Bits 0 and 1 Refer to Table 131 for bit rate description.
2
CPHA
1-0
SPR1:0
Reset Value = 0001 0100b
Note: 1. When the SPI is disabled, SCK outputs high level.
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Table 133. SPSTA Register SPSTA (S:C4h) - SPI Status Register
7 SPIF Bit Number 6 WCOL 5 4 MODF 3 2 1 0 -
Bit Mnemonic Description SPI Interrupt Flag Set by hardware when an 8-bit shift is completed. Cleared by hardware when reading or writing SPDAT after reading SPSTA. Write Collision Flag Set by hardware to indicate that a collision has been detected. Cleared by hardware to indicate that no collision has been detected. Reserved The value read from this bit is indeterminate. Do not set this bit. Mode Fault Set by hardware to indicate that the SS pin is at an appropriate level. Cleared by hardware to indicate that the SS pin is at an inappropriate level. Reserved The value read from these bits is indeterminate. Do not set these bits.
7
SPIF
6
WCOL
5
-
4
MODF
3-0
-
Reset Value = 00000 0000b Table 134. SPDAT Register SPDAT (S:C5h) - Synchronous Serial Data Register
7 SPD7 Bit Number 7-0 6 SPD6 5 SPD5 4 SPD4 3 SPD3 2 SPD2 1 SPD1 0 SPD0
Bit Mnemonic Description SPD7:0 Synchronous Serial Data.
Reset Value = XXXX XXXXb
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Two-wire Interface (TWI) Controller
The AT8xC51SND1C implements a TWI controller supporting the four standard master and slave modes with multimaster capability. Thus, it allows connection of slave devices like LCD controller, audio DAC, etc., but also external master controlling where the AT8xC51SND1C is used as a peripheral of a host. The TWI bus is a bi-directional TWI serial communication standard. It is designed primarily for simple but efficient integrated circuit control. The system is comprised of 2 lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them. The serial data transfer is limited to 100 Kbit/s in low speed mode, however, some higher bit rates can be achieved depending on the oscillator frequency. Various communication configurations can be designed using this bus. Figure 123 shows a typical TWI bus configuration using the AT8xC51SND1C in master and slave modes. All the devices connected to the bus can be master and slave. Figure 123. Typical TWI Bus Configuration
AT8xC51SND1C Master/Slave
Rp P1.6/SCL P1.7/SDA Rp SCL SDA
LCD Display
Audio DAC
HOST Microprocessor
Description
The CPU interfaces to the TWI logic via the following four 8-bit special function registers: the Synchronous Serial Control register (SSCON SFR, see Table 142), the Synchronous Serial Data register (SSDAT SFR, see Table 144), the Synchronous Serial Status register (SSSTA SFR, see Table 143) and the Synchronous Serial Address register (SSADR SFR, see Table 145). SSCON is used to enable the controller, to program the bit rate (see Table 142), to enable slave modes, to acknowledge or not a received data, to send a START or a STOP condition on the TWI bus, and to acknowledge a serial interrupt. A hardware reset disables the TWI controller. SSSTA contains a status code which reflects the status of the TWI logic and the TWI bus. The three least significant bits are always zero. The five most significant bits contains the status code. There are 26 possible status codes. When SSSTA contains F8h, no relevant state information is available and no serial interrupt is requested. A valid status code is available in SSSTA after SSI is set by hardware and is still present until SSI has been reset by software. Table 136 to Table 128 give the status for both master and slave modes and miscellaneous states. SSDAT contains a Byte of serial data to be transmitted or a Byte which has just been received. It is addressable while it is not in process of shifting a Byte. This occurs when TWI logic is in a defined state and the serial interrupt flag is set. Data in SSDAT remains stable as long as SSI is set. While data is being shifted out, data on the bus is simultaneously shifted in; SSDAT always contains the last Byte present on the bus. SSADR may be loaded with the 7 - bit slave address (7 most significant bits) to which the controller will respond when programmed as a slave transmitter or receiver. The LSB is used to enable general call address (00h) recognition. Figure 124 shows how a data transfer is accomplished on the TWI bus.
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Figure 124. Complete Data Transfer on TWI Bus
SDA
MSB Slave Address R/W ACK direction signal bit from receiver 8 9 1 Nth data Byte ACK signal from receiver 8 9 P/S
SCL
S
1
2
2
Clock Line Held Low While Serial Interrupts Are Serviced
The four operating modes are: * * * * Master transmitter Master receiver Slave transmitter Slave receiver
Data transfer in each mode of operation are shown in Figure 125 through Figure 128. These figures contain the following abbreviations: A A Data S P MR MT SLA GCA R W Acknowledge bit (low level at SDA) Not acknowledge bit (high level on SDA) 8-bit data Byte START condition STOP condition Master Receive Master Transmit Slave Address General Call Address (00h) Read bit (high level at SDA) Write bit (low level at SDA)
In Figure 125 through Figure 128, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in SSSTA. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. When the serial interrupt routine is entered, the status code in SSSTA is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in Table 136 through Table 128.
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Bit Rate
The bit rate can be selected from seven predefined bit rates or from a programmable bit rate generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see Table 142). The predefined bit rates are derived from the peripheral clock (FPER) issued from the Clock Controller block as detailed in section "Oscillator", page 12, while bit rate generator is based on timer 1 overflow output. Table 135. Serial Clock Rates
SSCRx 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 FPER = 6 MHz 47 53.5 62.5 75 12.5 100 200(1) 0.5 < < 125(1) Bit Frequency (kHz) FPER = 8 MHz 62.5 71.5 83 100 16.5 133.3(1) 266.7(1) FPER = 10 MHz 78.125 89.3 104.2(1) 125(1) 20.83 166.7(1) 333.3(1) FPER Divided By 256 224 192 160 960 120 60 96 (256 - reload value Timer 1)
0.67 < < 166.7(1) 0.81 < < 208.3(1)
Note:
1. These bit rates are outside of the low speed standard specification limited to 100 kHz but can be used with high speed TWI components limited to 400 kHz.
Master Transmitter Mode
In the master transmitter mode, a number of data Bytes are transmitted to a slave receiver (see Figure 125). Before the master transmitter mode can be entered, SSCON must be initialized as follows:
SSCR2 Bit Rate SSPE 1 SSSTA 0 SSSTO 0 SSI 0 SSAA X SSCR1 Bit Rate SSCR0 Bit Rate
SSCR2:0 define the serial bit rate (see Table 135). SSPE must be set to enable the controller. SSSTA, SSSTO and SSI must be cleared. The master transmitter mode may now be entered by setting the SSSTA bit. The TWI logic will now monitor the TWI bus and generate a START condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SSI bit in SSCON) is set, and the status code in SSSTA is 08h. This status must be used to vector to an interrupt routine that loads SSDAT with the slave address and the data direction bit (SLA+W). The serial interrupt flag (SSI) must then be cleared before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, SSI is set again and a number of status code in SSSTA are possible. There are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (SSAA = logic 1). The appropriate action to be taken for each of these status code is detailed in Table 136. This scheme is repeated until a STOP condition is transmitted. SSPE and SSCR2:0 are not affected by the serial transfer and are not referred to in Table 136. After a repeated START condition (state 10h) the controller may switch to the master receiver mode by loading SSDAT with SLA+R.
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Master Receiver Mode In the master receiver mode, a number of data Bytes are received from a slave transmitter (see Figure 126). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt routine must load SSDAT with the 7 - bit slave address and the data direction bit (SLA+R). The serial interrupt flag (SSI) must then be cleared before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag is set again and a number of status code in SSSTA are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (SSAA = logic 1). The appropriate action to be taken for each of these status code is detailed in Table 128. This scheme is repeated until a STOP condition is transmitted. SSPE and SSCR2:0 are not affected by the serial transfer and are not referred to in Table 128. After a repeated START condition (state 10h) the controller may switch to the master transmitter mode by loading SSDAT with SLA+W. Slave Receiver Mode In the slave receiver mode, a number of data Bytes are received from a master transmitter (see Figure 127). To initiate the slave receiver mode, SSADR and SSCON must be loaded as follows:
SSA6 SSA5 SSA4 SSA3 Own Slave Address SSA2 SSA1 SSA0 SSGC X
The upper 7 bits are the addresses to which the controller will respond when addressed by a master. If the LSB (SSGC) is set, the controller will respond to the general call address (00h); otherwise, it ignores the general call address.
SSCR2 X SSPE 1 SSSTA 0 SSSTO 0 SSI 0 SSAA 1 SSCR1 X SSCR0 X
SSCR2:0 have no effect in the slave mode. SSPE must be set to enable the controller. The SSAA bit must be set to enable the own slave address or the general call address acknowledgment. SSSTA, SSSTO and SSI must be cleared. When SSADR and SSCON have been initialized, the controller waits until it is addressed by its own slave address followed by the data direction bit which must be logic 0 (W) for operating in the slave receiver mode. After its own slave address and the W bit has been received, the serial interrupt flag is set and a valid status code can be read from SSSTA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status code is detailed in Table 128 and Table 140. The slave receiver mode may also be entered if arbitration is lost while the controller is in the master mode (see states 68h and 78h). If the SSAA bit is reset during a transfer, the controller will return a not acknowledge (logic 1) to SDA after the next received data Byte. While SSAA is reset, the controller does not respond to its own slave address. However, the TWI bus is still monitored and address recognition may be resumed at any time by setting SSAA. This means that the SSAA bit may be used to temporarily isolate the controller from the TWI bus.
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Slave Transmitter Mode
In the slave transmitter mode, a number of data Bytes are transmitted to a master receiver (see Figure 128). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON have been initialized, the controller waits until it is addressed by its own slave address followed by the data direction bit which must be logic 1 (R) for operating in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag is set and a valid status code can be read from SSSTA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status code is detailed in Table 140. The slave transmitter mode may also be entered if arbitration is lost while the controller is in the master mode (see state B0h). If the SSAA bit is reset during a transfer, the controller will transmit the last Byte of the transfer and enter state C0h or C8h. The controller is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1's as serial data. While SSAA is reset, the controller does not respond to its own slave address. However, the TWI bus is still monitored and address recognition may be resumed at any time by setting SSAA. This means that the SSAA bit may be used to temporarily isolate the controller from the TWI bus.
Miscellaneous States
There are 2 SSSTA codes that do not correspond to a defined TWI hardware state (see Table 141). These are discussed below. Status F8h indicates that no relevant information is available because the serial interrupt flag is not yet set. This occurs between other states and when the controller is not involved in a serial transfer. Status 00h indicates that a bus error has occurred during a serial transfer. A bus error is caused when a START or a STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address Byte, a data Byte, or an acknowledge bit. When a bus error occurs, SSI is set. To recover from a bus error, the SSSTO flag must be set and SSI must be cleared. This causes the controller to enter the not addressed slave mode and to clear the SSSTO flag (no other bits in S1CON are affected). The SDA and SCL lines are released and no STOP condition is transmitted.
Note: The TWI controller interfaces to the external TWI bus via 2 port 1 pins: P1.6/SCL (serial clock line) and P1.7/SDA (serial data line). To avoid low level asserting and conflict on these lines when the TWI controller is enabled, the output latches of P1.6 and P1.7 must be set to logic 1.
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Figure 125. Format and States in the Master Transmitter Mode MT
Successful transmission to a slave receiver
S
SLA
W
A
Data
A
P
08h
Next transfer started with a repeated start condition
18h
28h
S SLA W
10h
R Not acknowledge received after the slave address A P
MR 20h
Not acknowledge received after a data Byte A P
30h
Arbitration lost in slave address or data Byte A or A
Other master continues
A or A
Other master continues
38h
Arbitration lost and addressed as slave A
Other master continues
38h
68h 78h B0h
To corresponding states in slave mode
From master to slave From slave to master
Data
A
Any number of data Bytes and their associated acknowledge bits This number (contained in SSSTA) corresponds to a defined state of the TWI bus
nnh
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Figure 126. Format and States in the Master Receiver Mode MR
Successful reception from a slave transmitter
S
SLA
R
A
Data
A
Data
A
P
08h
Next transfer started with a repeated start condition
40h
50h
58h
S SLA R
10h
W Not acknowledge received after the slave address A P
MT 48h
Arbitration lost in slave address or data Byte A or A
Other master continues
A
Other master continues
38h
Arbitration lost and addressed as slave A
Other master continues
38h
68h 78h B0h
To corresponding states in slave mode
From master to slave From slave to master
Data
A
Any number of data Bytes and their associated acknowledge bits This number (contained in SSSTA) corresponds to a defined state of the TWI bus
nnh
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Figure 127. Format and States in the Slave Receiver Mode
Reception of the own slave address and one or more data Bytes. All are acknowledged S SLA W A Data A Data A P or S
60h
Last data Byte received is not acknowledged
80h
80h
A
A0h
P or S
88h
Arbitration lost as master and addressed as slave A
68h
Reception of the general call address and one or more data Bytes General Call A Data A Data A P or S
70h
Last data Byte received is not acknowledged
90h
90h
A
A0h
P or S
98h
Arbitration lost as master and addressed as slave by general call A
78h
From master to slave From slave to master
Data
A
Any number of data Bytes and their associated acknowledge bits This number (contained in SSSTA) corresponds to a defined state of the TWI bus
nnh
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Figure 128. Format and States in the Slave Transmitter Mode
Reception of the own slave address and transmission of one or more data Bytes. S SLA R A Data A Data A P or S
A8h
Arbitration lost as master and addressed as slave A
B8h
C0h
B0h
Last data Byte transmitted. Switched to not addressed slave (SSAA = 0). A All 1's P or S
C8h
From master to slave From slave to master
Data
A
Any number of data Bytes and their associated acknowledge bits This number (contained in SSSTA) corresponds to a defined state of the TWI bus
nnh
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Table 136. Status for Master Transmitter Mode
Application Software Response Status Code SSSTA 08h To SSCON Status of the TWI Bus and TWI Hardware To/From SSDAT A START condition has Write SLA+W been transmitted A repeated START condition has been transmitted Write SLA+W Write SLA+R SSSTA X SSSTO 0 SSI 0 SSAA X Next Action Taken by TWI Hardware SLA+W will be transmitted.
X X
0 0
0 0
X X
SLA+W will be transmitted. SLA+R will be transmitted. Logic will switch to master receiver mode Data Byte will be transmitted. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Data Byte will be transmitted. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Data Byte will be transmitted. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Data Byte will be transmitted. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. TWI bus will be released and not addressed slave mode will be entered. A START condition will be transmitted when the bus becomes free.
10h
Write data Byte SLA+W has been transmitted; ACK has been received No SSDAT action No SSDAT action No SSDAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
18h
Write data Byte SLA+W has been transmitted; NOT ACK has been received No SSDAT action No SSDAT action No SSDAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
20h
Write data Byte Data Byte has been transmitted; ACK has been received No SSDAT action No SSDAT action No SSDAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
28h
Write data Byte Data Byte has been transmitted; NOT ACK has been received No SSDAT action No SSDAT action No SSDAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
30h
No SSDAT action 38h Arbitration lost in SLA+W or data Bytes No SSDAT action
0 1
0 0
0 0
X X
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Table 137. Status for Master Receiver Mode
Application Software Response Status Code SSSTA 08h To SSCON Status of the TWI Bus and TWI Hardware To/From SSDAT A START condition has Write SLA+R been transmitted A repeated START condition has been transmitted Write SLA+R Write SLA+W SSSTA X SSSTO 0 SSI 0 SSAA X Next Action Taken by TWI Hardware SLA+R will be transmitted.
X X
0 0
0 0
X X
SLA+R will be transmitted. SLA+W will be transmitted. Logic will switch to master transmitter mode. TWI bus will be released and not addressed slave mode will be entered. A START condition will be transmitted when the bus becomes free. Data Byte will be received and NOT ACK will be returned. Data Byte will be received and ACK will be returned. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Data Byte will be received and NOT ACK will be returned. Data Byte will be received and ACK will be returned. Repeated START will be transmitted. STOP condition will be transmitted and SSSTO flag will be reset. STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset.
10h
38h
Arbitration lost in SLA+R or NOT ACK bit SLA+R has been transmitted; ACK has been received
No SSDAT action No SSDAT action
0 1 0 0 1 0 1 0 0 1 0 1
0 0 0 0 0 1 1 0 0 0 1 1
0 0 0 0 0 0 0 0 0 0 0 0
X X 0 1 X X X 0 1 X X X
No SSDAT action No SSDAT action No SSDAT action
40h
48h
SLA+R has been transmitted; NOT ACK has been received
No SSDAT action No SSDAT action
50h
Data Byte has been received; ACK has been returned
Read data Byte Read data Byte Read data Byte
58h
Data Byte has been received; NOT ACK has been returned
Read data Byte Read data Byte
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Table 138. Status for Slave Receiver Mode with Own Slave Address
Application Software Response Status Code SSSTA To SSCON Status of the TWI Bus and TWI Hardware To/From SSDAT Own SLA+W has been received; ACK has been returned Arbitration lost in SLA+R/W as master; own SLA+W has been received; ACK has been returned Previously addressed with own SLA+W; data has been received; ACK has been returned No SSDAT action No SSDAT action No SSDAT action X No SSDAT action X Read data Byte X Read data Byte X Read data Byte Read data Byte Previously addressed with own SLA+W; data has been received; NOT ACK has been returned 0 0 Read data Byte 1 Read data Byte 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 Switched to the not addressed slave mode; no recognition of own SLA or GCA. Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if SSGC = logic 1. Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free. Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if SSGC = logic 1. A START condition will be transmitted when the bus becomes free. Switched to the not addressed slave mode; no recognition of own SLA or GCA. Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if SSGC = logic 1. Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free. Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if SSGC = logic 1. A START condition will be transmitted when the bus becomes free. 0 0 0 0 0 1 Data Byte will be received and NOT ACK will be returned. Data Byte will be received and ACK will be returned. 0 0 0 SSSTA X X SSSTO 0 0 SSI 0 0 SSAA 0 1 Next Action Taken by TWI Hardware Data Byte will be received and NOT ACK will be returned. Data Byte will be received and ACK will be returned. Data Byte will be received and NOT ACK will be returned. Data Byte will be received and ACK will be returned.
60h
68h
80h
88h
No SSDAT action No SSDAT action A STOP condition or repeated START condition has been received while still addressed as slave 0 0 No SSDAT action 1 No SSDAT action 1 0 0 1 0 0 0 0 0 0 0 0 1
A0h
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Table 139. Status for Slave Receiver Mode with General Call Address
Application Software Response Status Code SSSTA To SSCON Status of the TWI Bus and TWI Hardware To/From SSDAT General call address has been received; ACK has been returned Arbitration lost in SLA+R/W as master; general call address has been received; ACK has been returned Previously addressed with general call; data has been received; ACK has been returned No SSDAT action No SSDAT action No SSDAT action X No SSDAT action X 0 0 1 0 0 0 SSSTA X X SSSTO 0 0 SSI 0 0 SSAA 0 1 Next Action Taken by TWI Hardware Data Byte will be received and NOT ACK will be returned. Data Byte will be received and ACK will be returned. Data Byte will be received and NOT ACK will be returned. Data Byte will be received and ACK will be returned.
70h
78h
Read data Byte X Read data Byte X Read data Byte Read data Byte 0 0 Read data Byte 1 Read data Byte 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0
Data Byte will be received and NOT ACK will be returned. Data Byte will be received and ACK will be returned.
90h
Switched to the not addressed slave mode; no recognition of own SLA or GCA. Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if SSGC = logic 1. Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free. Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if SSGC = logic 1. A START condition will be transmitted when the bus becomes free. Switched to the not addressed slave mode; no recognition of own SLA or GCA. Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if SSGC = logic 1. Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free. Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if SSGC = logic 1. A START condition will be transmitted when the bus becomes free.
98h
Previously addressed with general call; data has been received; NOT ACK has been returned
No SSDAT action No SSDAT action A STOP condition or repeated START condition has been received while still addressed as slave 0 0 No SSDAT action 1 No SSDAT action 1 0 0 1 0 0 0 0 0 0 0 0 1
A0h
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Table 140. Status for Slave Transmitter Mode
Application Software Response Status Code SSSTA Status of the TWI Bus and TWI Hardware To/From SSDAT Own SLA+R has been received; ACK has been returned Arbitration lost in SLA+R/W as master; own SLA+R has been received; ACK has been returned Data Byte in SSDAT has been transmitted; ACK has been received Write data Byte Write data Byte Write data Byte X Write data Byte X Write data Byte Write data Byte No SSDAT action No SSDAT action Data Byte in SSDAT has been transmitted; NOT ACK has been received 0 0 No SSDAT action 1 No SSDAT action 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 Last data Byte will be transmitted. Data Byte will be transmitted. Switched to the not addressed slave mode; no recognition of own SLA or GCA. Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if SSGC = logic 1. Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free. Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if SSGC = logic 1. A START condition will be transmitted when the bus becomes free. Switched to the not addressed slave mode; no recognition of own SLA or GCA. Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if SSGC = logic 1. Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free. Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if SSGC = logic 1. A START condition will be transmitted when the bus becomes free. 0 0 0 Data Byte will be transmitted. SSSTA X X To SSCON SSSTO 0 0 SSI 0 0 SSAA 0 1 Next Action Taken by TWI Hardware Last data Byte will be transmitted. Data Byte will be transmitted. Last data Byte will be transmitted.
A8h
B0h
X X
0 0
0 0
0 1
B8h
C0h
No SSDAT action No SSDAT action Last data Byte in SSDAT has been transmitted (SSAA= 0); ACK has been received 0 0 No SSDAT action 1 No SSDAT action 1 0 0 1 0 0 0 0 0 0 0 0 1
C8h
Table 141. Status for Miscellaneous States
Application Software Response Status Code SSSTA To SSCON Status of the TWI Bus and TWI Hardware To/From SSDAT No relevant state information available; SSI = 0 Bus error due to an illegal START or STOP condition No SSDAT action No SSCON action SSSTA SSSTO SSI SSAA Next Action Taken by TWI Hardware Wait or proceed current transfer.
F8h
No SSDAT action 0 1 0 X
00h
Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released and SSSTO is reset.
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Registers
Table 142. SSCON Register SSCON (S:93h) - Synchronous Serial Control Register
7 SSCR2 Bit Number 7 6 SSPE 5 SSSTA 4 SSSTO 3 SSI 2 SSAA 1 SSCR1 0 SSCR0
Bit Mnemonic Description SSCR2 Synchronous Serial Control Rate Bit 2 Refer to Table 135 for rate description. Synchronous Serial Peripheral Enable Bit Set to enable the controller. Clear to disable the controller. Synchronous Serial Start Flag Set to send a START condition on the bus. Clear not to send a START condition on the bus. Synchronous Serial Stop Flag Set to send a STOP condition on the bus. Clear not to send a STOP condition on the bus. Synchronous Serial Interrupt Flag Set by hardware when a serial interrupt is requested. Must be cleared by software to acknowledge interrupt. Synchronous Serial Assert Acknowledge Flag Set to enable slave modes. Slave modes are entered when SLA or GCA (if SSGC set) is recognized. Clear to disable slave modes. Master Receiver Mode in progress Clear to force a not acknowledge (high level on SDA). Set to force an acknowledge (low level on SDA). Master Transmitter Mode in progress This bit has no specific effect when in master transmitter mode. Slave Receiver Mode in progress Clear to force a not acknowledge (high level on SDA). Set to force an acknowledge (low level on SDA). Slave Transmitter Mode in progress Clear to isolate slave from the bus after last data Byte transmission. Set to enable slave mode. Synchronous Serial Control Rate Bit 1 Refer to Table 135 for rate description. Synchronous Serial Control Rate Bit 0 Refer to Table 135 for rate description.
6
SSPE
5
SSSTA
4
SSSTO
3
SSI
2
SSAA
1
SSCR1
0
SSCR0
Reset Value = 0000 0000b
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Table 143. SSSTA Register SSSTA (S:94h) - Synchronous Serial Status Register
7 SSC4 Bit Number 7:3 2:0 6 SSC3 5 SSC2 4 SSC1 3 SSC0 2 0 1 0 0 0
Bit Mnemonic Description SSC4:0 0 Synchronous Serial Status Code Bits 0 to 4 Refer to Table 136 to Table 128 for status description. Always 0.
Reset Value = F8h Table 144. SSDAT Register SSDAT (S:95h) - Synchronous Serial Data Register
7 SSD7 Bit Number 7:1 0 6 SSD6 5 SSD5 4 SSD4 3 SSD3 2 SSD2 1 SSD1 0 SSD0
Bit Mnemonic Description SSD7:1 SSD0 Synchronous Serial Address bits 7 to 1 or Synchronous Serial Data Bits 7 to 1 Synchronous Serial Address bit 0 (R/W) or Synchronous Serial Data Bit 0
Reset Value = 1111 1111b Table 145. SSADR Register SSADR (S:96h) - Synchronous Serial Address Register
7 SSA7 Bit Number 7:1 6 SSA6 5 SSA5 4 SSA4 3 SSA3 2 SSA2 1 SSA1 0 SSGC
Bit Mnemonic Description SSA7:1 Synchronous Serial Slave Address Bits 7 to 1 Synchronous Serial General Call Bit Set to enable the general call address recognition. Clear to disable the general call address recognition.
0
SSGC
Reset Value = 1111 1110b
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Analog to Digital Converter
Description
The AT8xC51SND1C implement a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). First channel of this ADC can be used for battery monitoring while the second one can be used for voice sampling at 8 kHz. The A/D converter interfaces with the C51 core through four special function registers: ADCON, the ADC control register (see Table 147); ADDH and ADDL, the ADC data registers (see Table 149 and Table 150); and ADCLK, the ADC clock register (see Table 148). As shown in Figure 129, the ADC is composed of a 10-bit cascaded potentiometric digital to analog converter, connected to the negative input of a comparator. The output voltage of this DAC is compared to the analog voltage stored in the Sample and Hold and coming from AIN0 or AIN1 input depending on the channel selected (see Table 146). The 10-bit ADDAT converted value (see formula in Figure 129) is delivered in ADDH and ADDL registers, ADDH is giving the 8 most significant bits while ADDL is giving the 2 least significant bits. ADDAT Figure 129. ADC Structure
ADCON.5 ADCON.3
ADEN
ADSST
ADCON.4
ADC CLOCK
ADEOC
CONTROL
ADC Interrupt Request EADC
IEN1.3
AIN1 AIN0
0 + 1 AVSS
8
ADDH ADDL
SAR Sample and Hold R/2R DAC
2
ADCS
ADCON.0
10
1023 V IN ADDAT = --------------------------V REF
AREFP AREFN
Figure 130 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer to the section "AC Characteristics". Figure 130. Timing Diagram CLK
TADCLK
ADEN
TSETUP
ADSST
TCONV
ADEOC
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Clock Generator The ADC clock is generated by division of the peripheral clock (see details in section "X2 Feature", page 12). The division factor is then given by ADCP4:0 bits in ADCLK register. Figure 131 shows the ADC clock generator and its calculation formula(1). Figure 131. ADC Clock Generator and Symbol Caution:
ADCLK
PER CLOCK /2
ADCD4:0
ADC Clock
ADC CLOCK
PERclk ADCclk = ------------------------2 ADCD Note:
ADC Clock Symbol
1. In all cases, the ADC clock frequency may be higher than the maximum FADCLK parameter reported in the section "Analog to Digital Converter", page 197. 2. The ADCD value of 0 is equivalent to an ADCD value of 32.
Channel Selection
The channel on which conversion is performed is selected by the ADCS bit in ADCON register according to Table 146. Table 146. ADC Channel Selection
ADCS 0 1 Channel AIN1 AIN0
Conversion Precision
The 10-bit precision conversion is achieved by stopping the CPU core activity during conversion for limiting the digital noise induced by the core. This mode called the Pseudo-Idle mode(1),(2) is enabled by setting the ADIDL bit in ADCON register(3). Thus, when conversion is launched (see Section "Conversion Launching", page 176), the CPU core is stopped until the end of the conversion (see Section "End Of Conversion", page 176). This bit is cleared by hardware at the end of the conversion.
Notes: 1. Only the CPU activity is frozen, peripherals are not affected by the Pseudo-Idle mode. 2. If some interrupts occur during the Pseudo-Idle mode, they will be delayed and processed, according to their priority after the end of the conversion. 3. Concurrently with ADSST bit.
Configuration
The ADC configuration consists in programming the ADC clock as detailed in the Section "Clock Generator", page 175. The ADC is enabled using the ADEN bit in ADCON register. As shown in Figure 93, user must wait the setup time (TSETUP) before launching any conversion.
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Figure 132. ADC Configuration Flow
ADC Configuration
Program ADC Clock ADCD4:0 = xxxxxb
Enable ADC ADIDL = x ADEN = 1
Wait Setup Time
Conversion Launching
The conversion is launched by setting the ADSST bit in ADCON register, this bit remains set during the conversion. As soon as the conversion is started, it takes 11 clock periods (TCONV) before the data is available in ADDH and ADDL registers. Figure 133. ADC Conversion Launching Flow
ADC Conversion Start
Select Channel ADCS = 0-1
Start Conversion ADSST = 1
End Of Conversion
The end of conversion is signalled by the ADEOC flag in ADCON register becoming set or by the ADSST bit in ADCON register becoming cleared. ADEOC flag can generate an interrupt if enabled by setting EADC bit in IEN1 register. This flag is set by hardware and must be reset by software.
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Registers
Table 147. ADCON Register ADCON (S:F3h) - ADC Control Register
7 Bit Number 7 6 ADIDL 5 ADEN 4 ADEOC 3 ADSST 2 1 0 ADCS
Bit Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. ADC Pseudo-Idle Mode Set to suspend the CPU core activity (pseudo-idle mode) during conversion. Clear by hardware at the end of conversion. ADC Enable Bit Set to enable the A to D converter. Clear to disable the A to D converter and put it in low power stand by mode. End Of Conversion Flag Set by hardware when ADC result is ready to be read. This flag can generate an interrupt. Must be cleared by software. Start and Status Bit Set to start an A to D conversion on the selected channel. Cleared by hardware at the end of conversion. Reserved The value read from these bits is always 0. Do not set these bits. Channel Selection Bit Set to select channel 0 for conversion. Clear to select channel 1 for conversion.
6
ADIDL
5
ADEN
4
ADEOC
3
ADSST
2-1
-
0
ADCS
Reset Value = 0000 0000b Table 148. ADCLK Register ADCLK (S:F2h) - ADC Clock Divider Register
7 Bit Number 7-5 6 5 4 ADCD4 3 ADCD3 2 ADCD2 1 ADCD1 0 ADCD0
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. ADC Clock Divider 5-bit divider for ADC clock generation.
4-0
ADCD4:0
Reset Value = 0000 0000b
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Table 149. ADDH Register ADDH (S:F5h Read Only) - ADC Data High Byte Register
7 ADAT9 Bit Number 7-0 6 ADAT8 5 ADAT7 4 ADAT6 3 ADAT5 2 ADAT4 1 ADAT3 0 ADAT2
Bit Mnemonic Description ADAT9:2 ADC Data 8 Most Significant Bits of the 10-bit ADC data.
Reset Value = 0000 0000b Table 150. ADDL Register ADDL (S:F4h Read Only) - ADC Data Low Byte Register
7 Bit Number 7-2 6 5 4 3 2 1 ADAT1 0 ADAT0
Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. ADC Data 2 Least Significant Bits of the 10-bit ADC data.
1-0
ADAT1:0
Reset Value = 0000 0000b
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Keyboard Interface
The AT8xC51SND1C implement a keyboard interface allowing the connection of a 4 x n matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1.3:0 and allow exit from idle and power down modes. The keyboard interfaces with the C51 core through 2 special function registers: KBCON, the keyboard control register (see Table 151); and KBSTA, the keyboard control and status register (see Table 152). The keyboard inputs are considered as 4 independent interrupt sources sharing the same interrupt vector. An interrupt enable bit (EKB in IEN1 register) allows global enable or disable of the keyboard interrupt (see Figure 134). As detailed in Figure 135 each keyboard input has the capability to detect a programmable level according to KINL3:0 bit value in KBCON register. Level detection is then reported in interrupt flags KINF3:0 in KBSTA register. A keyboard interrupt is requested each time one of the four flags is set, i.e. the input level matches the programmed one. Each of these four flags can be masked by software using KINM3:0 bits in KBCON register and is cleared by reading KBSTA register. This structure allows keyboard arrangement from 1 by n to 4 by n matrix and allow usage of KIN inputs for any other purposes. Figure 134. Keyboard Interface Block Diagram
KIN0 KIN1 KIN2 KIN3 Input Circuitry Input Circuitry Input Circuitry EKB Input Circuitry
IEN1.4
Description
Keyboard Interface Interrupt Request
Figure 135. Keyboard Input Circuitry
0
KIN3:0
1
KINF3:0
KBSTA.3:0
KINM3:0 KINL3:0
KBCON.7:4 KBCON.3:0
Power Reduction Mode
KIN3:0 inputs allow exit from idle and power-down modes as detailed in section "Power Management", page 46. To enable this feature, KPDE bit in KBSTA register must be set to logic 1. Due to the asynchronous keypad detection in power down mode (all clocks are stopped), exit may happen on parasitic key press. In this case, no key is detected and software must enter power down again.
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Table 151. KBCON Register KBCON (S:A3h) - Keyboard Control Register
7 KINL3 Bit Number 6 KINL2 5 KINL1 4 KINL0 3 KINM3 2 KINM2 1 KINM1 0 KINM0
Bit Mnemonic Description Keyboard Input Level Bit Set to enable a high level detection on the respective KIN3:0 input. Clear to enable a low level detection on the respective KIN3:0 input. Keyboard Input Mask Bit Set to prevent the respective KINF3:0 flag from generating a keyboard interrupt. Clear to allow the respective KINF3:0 flag to generate a keyboard interrupt.
7-4
KINL3:0
3-0
KINM3:0
Reset Value = 0000 1111b Table 152. KBSTA Register KBSTA (S:A4h) - Keyboard Control and Status Register
7 KPDE Bit Number 6 5 4 3 KINF3 2 KINF2 1 KINF1 0 KINF0
Bit Mnemonic Description Keyboard Power Down Enable Bit Set to enable exit of power down mode by the keyboard interrupt. Clear to disable exit of power down mode by the keyboard interrupt. Reserved The value read from these bits is always 0. Do not set these bits. Keyboard Input Interrupt Flag Set by hardware when the respective KIN3:0 input detects a programmed level. Cleared when reading KBSTA.
7
KPDE
6-4
-
3-0
KINF3:0
Reset Value = 0000 0000b
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Electrical Characteristics
Absolute Maximum Rating
Storage Temperature ......................................... -65 to +150C Voltage on any other Pin to VSS
.................................... -0.3
*NOTICE:
to +4.0 V
IOL per I/O Pin ................................................................. 5 mA Power Dissipation ............................................................. 1 W Operating Conditions Ambient Temperature Under Bias........................ -40 to +85C VDD ......................................................................................................... 2.7 to 3.3V
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "operating conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
DC Characteristics
Digital Logic Table 153. Digital DC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol VIL VIH1(2) VIH2 VOL1 Parameter Input Low Voltage Input High Voltage (except RST, X1) Input High Voltage (RST, X1) Output Low Voltage (except P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) Output Low Voltage (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) Output High Voltage (P1, P2, P3, P4 and P5) Output High Voltage (P0, P2 address mode, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT, D+, D-) Logical 0 Input Current (P1, P2, P3, P4 and P5) Input Leakage Current (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) Logical 1 to 0 Transition Current (P1, P2, P3, P4 and P5) Pull-Down Resistor Pin Capacitance VDD Data Retention Limit 50 90 10 1.8 VDD - 0.7 Min -0.5 0.2*VDD + 1.1 0.7*VDD Typ(1) Max 0.2*VDD - 0.1 VDD VDD + 0.5 0.45 Units V V V Test Conditions
V
IOL= 1.6 mA
VOL2
0.45
V
IOL= 3.2 mA
VOH1
V
IOH= -30 A
VOH2
VDD - 0.7
V
IOH= -3.2 mA
IIL
-50
A
Vin = 0.45 V
ILI
10
A
0.45< VIN< VDD
ITL RRST CIO VRET
-650 200
A k pF V
Vin = 2.0 V
TA= 25C
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Table 153. Digital DC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol Parameter Min Typ(1) Max X1 / X2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 Units Test Conditions VDD < 3.3 V mA 12 MHz 16 MHz 20 MHz VDD < 3.3 V AT83C51SND1C Operating Current TBD TBD mA 12 MHz 16 MHz 20 MHz VDD < 3.3 V mA 12 MHz 16 MHz 20 MHz VDD < 3.3 V AT83C51SND1C Idle Mode Current TBD TBD mA 12 MHz 16 MHz 20 MHz VRET < VDD < 3.3 V VRET < VDD < 3.3 V VDD < 3.3 V
AT89C51SND1C Operating Current IDD
(3)
AT89C51SND1C Idle Mode Current IDL
(3)
X1 / X2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13
AT89C51SND1C Power-Down Mode Current IPD AT83C51SND1C Power-Down Mode Current IFP AT89C51SND1C Flash Programming Current
20
500
A A mA
TBD
TBD
15
Notes:
1. Typical values are obtained using VDD= 3 V and TA= 25C. They are not tested and there is no guarantee on these values. 2. Flash retention is guaranteed with the same formula for VDD min down to 0V. 3. See Table 154 for typical consumption in player mode.
Table 154. Typical Reference Design AT89C51SND1C Power Consumption
Player Mode Stop IDD 10 mA Test Conditions AT89C51SND1C at 16 MHz, X2 mode, VDD= 3 V No song playing AT89C51SND1C at 16 MHz, X2 mode, VDD= 3 V MP3 Song with Fs= 44.1 KHz, at any bit rates (Variable Bit Rate)
Playing
30 mA
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IDD, IDL and IPD Test Conditions Figure 136. IDD Test Condition, Active Mode
VDD VDD
RST
VDD PVDD UVDD AVDD
IDD
(NC) Clock Signal
X2 X1 P0 VSS PVSS UVSS AVSS TST
VDD
VSS
All other pins are unconnected
Figure 137. IDL Test Condition, Idle Mode
VDD
RST
VSS
VDD PVDD UVDD AVDD
IDL
(NC) Clock Signal
X2 X1 P0 VSS PVSS UVSS AVSS TST
VDD
VSS
All other pins are unconnected
Figure 138. IPD Test Condition, Power-Down Mode
VDD
RST
VSS
VDD PVDD UVDD AVDD P0 MCMD MDAT TST
IPD
VDD
(NC)
X2 X1 VSS PVSS UVSS AVSS
VSS
All other pins are unconnected
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A to D Converter Table 155. A to D Converter DC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol AVDD AIDD Parameter Analog Supply Voltage Analog Operating Supply Current Min 2.7 Typ Max 3.3 Units V A AVDD= 3.3V AIN1:0= 0 to AVDD ADEN= 1 AVDD= 3.3V ADEN= 0 or PD= 1 Test Conditions
600
AIPD AVIN AVREF RREF CIA
Analog Standby Current Analog Input Voltage Reference Voltage AREFN AREFP AREF Input Resistance Analog Input capacitance AVSS AVSS 2.4 10
2 AVDD
A V
V AVDD 30 10 K pF TA= 25C TA= 25C
Oscillator & Crystal Schematic Figure 139. Crystal Connection
X1 C1 Q C2
VSS
X2
Note:
For operation with most standard crystals, no external components are needed on X1 and X2. It may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10 pF). X1 and X2 may not be used to drive other circuits.
Parameters
Table 156. Oscillator & Crystal Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol CX1 CX2 CL DL F RS CS Parameter Internal Capacitance (X1 - VSS) Internal Capacitance (X2 - VSS) Equivalent Load Capacitance (X1 - X2) Drive Level Crystal Frequency Crystal Series Resistance Crystal Shunt Capacitance Min Typ 10 10 5 50 20 40 6 Max Unit pF pF pF W MHz pF
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Phase Lock Loop Schematic Figure 140. PLL Filter Connection
FILT R C1
VSS VSS
C2
Parameters
Table 157. PLL Filter Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol R C1 C2 Filter Resistor Filter Capacitance 1 Filter Capacitance 2 Parameter Min Typ 100 10 2.2 Max Unit nF nF
In System Programming Schematic Figure 141. ISP Pull-Down Connection
ISP RISP
VSS
Parameters
Table 158. ISP Pull-Down Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol RISP Parameter ISP Pull-Down Resistor Min Typ 2.2 Max Unit K
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AC Characteristics
External 8-bit Bus Cycles Definition of Symbols Table 159. External 8-bit Bus Cycles Timing Symbol Definitions
Signals A D L Q R W Address Data In ALE Data Out RD WR H L V X Z Conditions High Low Valid No Longer Valid Floating
Timings
Test conditions: capacitive load on all pins= 50 pF. Table 160. External 8-bit Bus Cycle - Data Read AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85C
Variable Clock Standard Mode Symbol TCLCL TLHLL TAVLL TLLAX TLLRL TRLRH TRHLH TAVDV TAVRL TRLDV TRLAZ TRHDX TRHDZ Parameter Clock Period ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low ALE Low to RD Low RD Pulse Width RD high to ALE High Address Valid to Valid Data In Address Valid to RD Low RD Low to Valid Data RD Low to Address Float Data Hold After RD High Instruction Float After RD High 0 2*TCLCL-25 4*TCLCL-30 5*TCLCL-30 0 0 TCLCL-25 Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 3*TCLCL-30 6*TCLCL-25 TCLCL-20 TCLCL+20 9*TCLCL-65 2*TCLCL-30 2.5*TCLCL-30 0 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 3*TCLCL-25 0.5*TCLCL-20 0.5*TCLCL+20 4.5*TCLCL-65 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
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Table 161. External 8-bit Bus Cycle - Data Write AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85C
Variable Clock Standard Mode Symbol TCLCL TLHLL TAVLL TLLAX TLLWL TWLWH TWHLH TAVWL TQVWH TWHQX Parameter Clock Period ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low ALE Low to WR Low WR Pulse Width WR High to ALE High Address Valid to WR Low Data Valid to WR High Data Hold after WR High Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 3*TCLCL-30 6*TCLCL-25 TCLCL-20 4*TCLCL-30 7*TCLCL-20 TCLCL-15 TCLCL+20 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 3*TCLCL-25 0.5*TCLCL-20 2*TCLCL-30 3.5*TCLCL-20 0.5*TCLCL-15 0.5*TCLCL+20 Max Unit ns ns ns ns ns ns ns ns ns ns
Waveforms
Figure 142. External 8-bit Bus Cycle - Data Read Waveforms
ALE TLHLL
TLLRL
TRLRH
TRHLH
RD TRLDV TRLAZ TAVLL P0 TLLAX A7:0 TAVRL TAVDV P2 A15:8 D7:0 Data In TRHDZ TRHDX
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Figure 143. External 8-bit Bus Cycle - Data Write Waveforms
ALE TLHLL
TLLWL
TWLWH
TWHLH
WR TAVWL TAVLL P0 TLLAX A7:0 TQVWH D7:0 Data Out P2 A15:8 TWHQX
External IDE 16-bit Bus Cycles Definition of Symbols Table 162. External IDE 16-bit Bus Cycles Timing Symbol Definitions
Signals A D L Q R W Address Data In ALE Data Out RD WR H L V X Z Conditions High Low Valid No Longer Valid Floating
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Timings Test conditions: capacitive load on all pins= 50 pF. Table 163. External IDE 16-bit Bus Cycle - Data Read AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85C
Variable Clock Standard Mode Symbol TCLCL TLHLL TAVLL TLLAX TLLRL TRLRH TRHLH TAVDV TAVRL TRLDV TRLAZ TRHDX TRHDZ Parameter Clock Period ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low ALE Low to RD Low RD Pulse Width RD high to ALE High Address Valid to Valid Data In Address Valid to RD Low RD Low to Valid Data RD Low to Address Float Data Hold After RD High Instruction Float After RD High 0 2*TCLCL-25 4*TCLCL-30 5*TCLCL-30 0 0 TCLCL-25 Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 3*TCLCL-30 6*TCLCL-25 TCLCL-20 TCLCL+20 9*TCLCL-65 2*TCLCL-30 2.5*TCLCL-30 0 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 3*TCLCL-25 0.5*TCLCL-20 0.5*TCLCL+20 4.5*TCLCL-65 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 164. External IDE 16-bit Bus Cycle - Data Write AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85C
Variable Clock Standard Mode Symbol TCLCL TLHLL TAVLL TLLAX TLLWL TWLWH TWHLH TAVWL TQVWH TWHQX Parameter Clock Period ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low ALE Low to WR Low WR Pulse Width WR High to ALE High Address Valid to WR Low Data Valid to WR High Data Hold after WR High Min 50 2*TCLCL-15 TCLCL-20 TCLCL-20 3*TCLCL-30 6*TCLCL-25 TCLCL-20 4*TCLCL-30 7*TCLCL-20 TCLCL-15 TCLCL+20 Max Variable Clock X2 Mode Min 50 TCLCL-15 0.5*TCLCL-20 0.5*TCLCL-20 1.5*TCLCL-30 3*TCLCL-25 0.5*TCLCL-20 2*TCLCL-30 3.5*TCLCL-20 0.5*TCLCL-15 0.5*TCLCL+20 Max Unit ns ns ns ns ns ns ns ns ns ns
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Waveforms
Figure 144. External IDE 16-bit Bus Cycle - Data Read Waveforms
ALE TLHLL
TLLRL
TRLRH
TRHLH
RD TRLDV TRLAZ TAVLL P0 TLLAX A7:0 TAVRL TAVDV P2 A15:8 D15:8(1) Data In D7:0 Data In TRHDZ TRHDX
Note:
1. D15:8 is written in DAT16H SFR.
Figure 145. External IDE 16-bit Bus Cycle - Data Write Waveforms
ALE TLHLL
TLLWL
TWLWH
TWHLH
WR TAVWL TAVLL P0 TLLAX A7:0 TQVWH D7:0 Data Out P2 A15:8 D15:8(1) Data Out TWHQX
Note:
1. D15:8 is the content of DAT16H SFR.
SPI Interface
Definition of Symbols Table 165. SPI Interface Timing Symbol Definitions
Signals C I O Clock Data In Data Out H L V X Z Conditions High Low Valid No Longer Valid Floating
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Timings Test conditions: capacitive load on all pins= 50 pF. Table 166. SPI Interface Master AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol Parameter Slave Mode TCHCH TCHCX TCLCX TSLCH, TSLCL TIVCL, TIVCH TCLIX, TCHIX TCLOV, TCHOV TCLOX, TCHOX TCLSH, TCHSH TSLOV TSHOX TSHSL TILIH TIHIL TOLOH TOHOL Clock Period Clock High Time Clock Low Time SS Low to Clock edge Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge Output Data Hold Time after Clock Edge SS High after Clock Edge SS Low to Output Data Valid Output Data Hold after SS High SS High to SS Low Input Rise Time Input Fall Time Output Rise time Output Fall Time Master Mode TCHCH TCHCX TCLCX TIVCL, TIVCH TCLIX, TCHIX TCLOV, TCHOV TCLOX, TCHOX TILIH TIHIL TOLOH TOHOL Clock Period Clock High Time Clock Low Time Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge Output Data Hold Time after Clock Edge Input Data Rise Time Input Data Fall Time Output Data Rise time Output Data Fall Time 0 2 2 50 50 2 0.8 0.8 20 20 40 TPER TPER TPER ns ns ns ns s s ns ns
(1)
Min
Max
Unit
2 0.8 0.8 100 40 40 40 0 0 50 50
TPER TPER TPER ns ns ns ns ns ns ns ns
2 2 100 100
s s ns ns
Note:
1. Value of this parameter depends on software.
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Waveforms
Figure 146. SPI Slave Waveforms (SSCPHA= 0)
SS (input) TSLCH TSLCL SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) TSLOV MISO (output) SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN TCLOV TCHOV BIT 6 TCHCH TCLCH
TCLSH TCHSH
TSHSL
TCHCX
TCLCX TCHCL
TCLOX TCHOX SLAVE LSB OUT
(1)
TSHOX
Note:
1. Not Defined but generally the MSB of the character which has just been received.
Figure 147. SPI Slave Waveforms (SSCPHA= 1)
SS (input) TSLCH TSLCL SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) TSLOV MISO (output)
(1)
TCHCH
TCLCH
TCLSH TCHSH
TSHSL
TCHCX
TCLCX TCHCL
TCHOV TCLOV BIT 6
TCHOX TCLOX SLAVE LSB OUT
TSHOX
SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX
MOSI (input)
MSB IN
BIT 6
LSB IN
Note:
1. Not Defined but generally the LSB of the character which has just been received.
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Figure 148. SPI Master Waveforms (SSCPHA= 0)
SS (output) TCHCH SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) TCLCH
TCHCX
TCLCX TCHCL
TIVCH TCHIX TIVCL TCLIX MSB IN BIT 6 TCLOV TCHOV LSB IN TCLOX TCHOX LSB OUT Port Data
MOSI (input)
MISO (output)
Port Data
MSB OUT
BIT 6
Note:
1. SS handled by software using general purpose port pin.
Figure 149. SPI Master Waveforms (SSCPHA= 1)
SS(1) (output) TCHCH SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) TCLCH
TCHCX
TCLCX TCHCL
TIVCH TCHIX TIVCL TCLIX
MOSI (input)
MSB IN TCLOV
BIT 6 TCLOX TCHOX BIT 6
LSB IN
MISO (output)
TCHOV Port Data MSB OUT
LSB OUT
Port Data
Note:
1. SS handled by software using general purpose port pin.
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Two-wire Interface Timings Table 167. TWI Interface AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85C
INPUT Min Max 14*TCLCL(4) 16*TCLCL(4) 14*TCLCL(4) 1 s 0.3 s 250 ns 250 ns 250 ns 0 ns 14*TCLCL(4) 14*TCLCL(4) 14*TCLCL(4) 1 s 0.3 s OUTPUT Min Max 4.0 s(1) 4.7 s(1) 4.0 s(1) -(2) 0.3 s(3) 20*TCLCL(4)- TRD 1 s(1) 8*TCLCL(4) 8*TCLCL(4) - TFC 4.7 s(1) 4.0 s(1) 4.7 s(1) -(2) 0.3 s(3)
Symbol THD; STA TLOW THIGH TRC TFC TSU; DAT1 TSU; DAT2 TSU; DAT3 THD; DAT TSU; STA TSU; STO TBUF TRD TFD
Parameter Start condition hold time SCL low time SCL high time SCL rise time SCL fall time Data set-up time SDA set-up time (before repeated START condition) SDA set-up time (before STOP condition) Data hold time Repeated START set-up time STOP condition set-up time Bus free time SDA rise time SDA fall time
Notes:
1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 s. 3. Spikes on the SDA and SCL lines with a duration of less than 3*TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL= 400 pF. 4. TCLCL= TOSC= one oscillator clock period.
Waveforms
Figure 150. Two Wire Waveforms
START or Repeated START condition Trd SDA (INPUT/OUTPUT) Tfd Trc SCL (INPUT/OUTPUT) Thd;STA Tlow Thigh Tsu;DAT1 Thd;DAT Tsu;DAT2 Tfc Tsu;STO Tsu;DAT3 0.7 VDD 0.3 VDD Tbuf Repeated START condition START condition STOP condition Tsu;STA 0.7 VDD 0.3 VDD
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MMC Interface Definition of symbols Table 168. MMC Interface Timing Symbol Definitions
Signals C D O Clock Data In Data Out H L V X Conditions High Low Valid No Longer Valid
Timings
Table 169. MMC Interface AC timings VDD = 2.7 to 3.3 V, TA = -40 to +85C, CL 100pF (10 cards)
Symbol TCHCH TCHCX TCLCX TCLCH TCHCL TDVCH TCHDX TCHOX TOVCH Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Input Data Valid to Clock High Input Data Hold after Clock High Output Data Hold after Clock High Output Data Valid to Clock High 3 3 5 5 Parameter Min 50 10 10 10 10 Max Unit ns ns ns ns ns ns ns ns ns
Waveforms
Figure 151. MMC Input-Output Waveforms
TCHCH TCHCX MCLK TCHCL TCHIX MCMD Input MDAT Input TCHOX MCMD Output MDAT Output TOVCH TCLCH TIVCH TCLCX
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Audio Interface Definition of symbols Table 170. Audio Interface Timing Symbol Definitions
Signals C O S Clock Data Out Data Select H L V X Conditions High Low Valid No Longer Valid
Timings
Table 171. Audio Interface AC timings VDD = 2.7 to 3.3 V, TA = -40 to +85C, CL 30pF
Symbol TCHCH TCHCX TCLCX TCLCH TCHCL TCLSV TCLOV Parameter Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Clock Low to Select Valid Clock Low to Data Valid 30 30 10 10 10 10 Min Max 325.5(1) Unit ns ns ns ns ns ns ns
Note:
1. 32-bit format with Fs= 48 KHz.
Waveforms
Figure 152. Audio Interface Waveforms
TCHCH TCHCX DCLK TCHCL TCLSV DSEL TCLOV DDAT Right Left TCLCH TCLCX
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Analog to Digital Converter Definition of symbols Table 172. Analog to Digital Converter Timing Symbol Definitions
Signals C E S Clock Enable (ADEN bit) Start Conversion (ADSST bit) H L Conditions High Low
Characteristics
Table 173. Analog to Digital Converter AC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol TCLCL TEHSH TSHSL DLe Parameter Clock Period Start-up Time Conversion Time Differential nonlinearity error(1)(2) Integral nonlinearity errorss(1)(3) Offset error(1)(4) Gain error(1)(5) Min 4 4 11*TCLCL 1 Max Unit s s s LSB
ILe OSe Ge
2 4 4
LSB LSB LSB
Notes:
1. AVDD= AVREFP= 3.0 V, AVSS= AVREFN= 0 V. ADC is monotonic with no missing code. 2. The differential non-linearity is the difference between the actual step width and the ideal step width (see Figure 154). 3. The integral non-linearity is the peak difference between the center of the actual step and the ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 154). 4. The offset error is the absolute difference between the straight line which fits the actual transfer curve (after removing of gain error), and the straight line which fits the ideal transfer curve (see Figure 154). 5. The gain error is the relative difference in percent between the straight line which fits the actual transfer curve (after removing of offset error), and the straight line which fits the ideal transfer curve (see Figure 154).
Waveforms
Figure 153. Analog to Digital Converter Internal Waveforms
CLK TCLCL ADEN Bit TEHSH ADSST Bit TSHSL
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Figure 154. Analog to Digital Converter Characteristics
Code Out
Offset Gain Error Error Ge OSe
1023 1022 1021 1020 1019 1018 Ideal Transfer curve
7 6 5 4 3 2 1 0 0 1 LSB (ideal) 1 Offset Error OSe 2 3 4 5 6 7 Center of a step
Example of an actual transfer curve
Integral non-linearity (ILe) Differential non-linearity (DLe)
1018 1019 1020 1021 1022 1023 1024
AVIN (LSB ideal)
Flash Memory Definition of symbols Table 174. Flash Memory Timing Symbol Definitions
Signals S R B ISP RST FBUSY flag L V X Conditions Low Valid No Longer Valid
Timings
Table 175. Flash Memory AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol TSVRL TRLSX TBHBL NFCY TFDR Parameter Input ISP Valid to RST Edge Input ISP Hold after RST Edge FLASH Internal Busy (Programming) Time Number of Flash Write Cycles Flash Data Retention Time 100K 10 Min 50 50 10 Typ Max Unit ns ns ms Cycle Years
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Waveforms Figure 155. FLASH Memory - ISP Waveforms
RST TSVRL ISP
(1)
TRLSX
Note:
1. ISP must be driven through a pull-down resistor (see Section "In System Programming", page 185).
Figure 156. FLASH Memory - Internal Busy Waveforms
FBUSY bit
TBHBL
External Clock Drive and Logic Level References Definition of symbols Table 176. External Clock Timing Symbol Definitions
Signals C Clock H L X Conditions High Low No Longer Valid
Timings
Table 177. External Clock AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85C
Symbol TCLCL TCHCX TCLCX TCLCH TCHCL TCR Clock Period High Time Low Time Rise Time Fall Time Cyclic Ratio in X2 mode Parameter Min 50 10 10 3 3 40 60 Max Unit ns ns ns ns ns %
Waveforms
Figure 157. External Clock Waveform
TCLCH VDD - 0.5 0.45 V VIH1 TCLCX TCHCL TCLCL TCHCX
VIL
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Figure 158. AC Testing Input/Output Waveforms
INPUTS VDD - 0.5 0.45 V 0.7 VDD 0.3 VDD OUTPUTS VIH min VIL max
Note:
1. During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a logic 0. 2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0.
Figure 159. Float Waveforms
VLOAD VLOAD + 0.1 V VLOAD - 0.1 V Timing Reference Points VOH - 0.1 V VOL + 0.1 V
Note:
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH= 20 mA.
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Ordering Information
Supply Voltage
3V 3V 3V 3V 3V 3V
Part Number
AT89C51SND1C-ROTIL AT89C51SND1C-7HTIL AT83SND1Cxxx(1)-ROTIL AT83SND1Cxxx(1)-7HTIL AT80SND1C-ROTIL AT80SND1C-7HTIL
Memory Size
64K Flash 64K Flash 64K ROM 64K ROM ROMless ROMless
Temperature Range
Industrial Industrial Industrial Industrial Industrial Industrial
Max Frequency
40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz
Package(2)
TQFP80 BGA81 TQFP80 BGA81 TQFP80 BGA81
Packing
Tray Tray Tray Tray Tray Tray
Notes:
1. Refers to ROM code. 2. PLCC84 package only available for development board.
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Package Information
TQFP80
202
AT8xC51SND1C
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AT8xC51SND1C
BGA81
203
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PLCC84
204
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Datasheet Change Log for AT8xC51SND1C
Changes from 4109D10/02 to 4109E-06/03
1. Additional information on AT83C51SND1C product. 2. Added BGA81 package. 3. Updated AC/DC characteristics for AT89C51SND1C product. 4. Changed the endurance of Flash to 100, 000 Write/Erase cycles. 5. Added note on Flash retention formula for VIH1, in Section "DC Characteristics", page 181.
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Table of Contents
Features ................................................................................................. 1 Description ............................................................................................ 1 Typical Applications ............................................................................. 2 Block Diagram ....................................................................................... 2 Pin Description ...................................................................................... 3
Pinouts ................................................................................................................. 3 Signals................................................................................................................... 6 Internal Pin Structure.......................................................................................... 11
Clock Controller .................................................................................. 12
Oscillator ............................................................................................................ 12 X2 Feature.......................................................................................................... 12 PLL ..................................................................................................................... 13 Registers ............................................................................................................. 15
Program/Code Memory ...................................................................... 17
ROM Memory Architecture ................................................................................. 17 Flash Memory Architecture ................................................................................ 18 Hardware Security System .................................................................................. 19 Boot Memory Execution ..................................................................................... 19 Preventing Flash Corruption............................................................................... 20 Registers ............................................................................................................. 21 Hardware Bytes ................................................................................................... 22
Data Memory ....................................................................................... 23
Internal Space .................................................................................................... 23 External Space .................................................................................................... 25 Dual Data Pointer ............................................................................................... 27 Registers ............................................................................................................ 28
Special Function Registers ................................................................ 30 Interrupt System ................................................................................. 36
Interrupt System Priorities .................................................................................. 36 External Interrupts .............................................................................................. 39 Registers ............................................................................................................. 40
Power Management ............................................................................ 46
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AT8xC51SND1C
Reset .................................................................................................................. 46 Reset Recommendation to Prevent Flash Corruption ........................................ 47 Idle Mode ............................................................................................................ 47 Power-down Mode.............................................................................................. 48 Registers..............................................................................................................50
Timers/Counters ................................................................................. 51
Timer/Counter Operations .................................................................................. 51 Timer Clock Controller ........................................................................................ 51 Timer 0................................................................................................................ 52 Timer 1................................................................................................................ 54 Interrupt .............................................................................................................. 55 Registers..............................................................................................................56
Watchdog Timer .................................................................................. 59
Description.......................................................................................................... 59 Watchdog Clock Controller ................................................................................. 59 Watchdog Operation............................................................................................60 Registers..............................................................................................................61
MP3 Decoder ....................................................................................... 62
Decoder .............................................................................................................. 62 Audio Controls .....................................................................................................64 Decoding Errors.................................................................................................. 64 Frame Information ...............................................................................................65 Ancillary Data...................................................................................................... 65 Interrupt ...............................................................................................................66 Registers..............................................................................................................68
Audio Output Interface ....................................................................... 73
Description.......................................................................................................... 73 Clock Generator...................................................................................................74 Data Converter ................................................................................................... 74 Audio Buffer ........................................................................................................ 75 MP3 Buffer.......................................................................................................... 76 Interrupt Request ................................................................................................ 76 MP3 Song Playing .............................................................................................. 76 Voice or Sound Playing ...................................................................................... 77 Registers..............................................................................................................78
Universal Serial Bus ........................................................................... 80
Description...........................................................................................................81 Configuration ...................................................................................................... 84 Read/Write Data FIFO ........................................................................................ 86 Bulk/Interrupt Transactions................................................................................. 87 Control Transactions........................................................................................... 91
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Isochronous Transactions....................................................................................92 Miscellaneous ......................................................................................................94 Suspend/Resume Management ..........................................................................95 USB Interrupt System ......................................................................................... 97 Registers..............................................................................................................99
MultiMedia Card Controller .............................................................. 109
Card Concept.................................................................................................... 109 Bus Concept ..................................................................................................... 109 Description........................................................................................................ 114 Clock Generator................................................................................................ 114 Command Line Controller................................................................................. 116 Data Line Controller...........................................................................................118 Interrupt .............................................................................................................124 Registers............................................................................................................125
IDE/ATAPI Interface .......................................................................... 131
Description........................................................................................................ 131 Registers........................................................................................................... 133
Serial I/O Port .................................................................................... 134
Mode Selection ................................................................................................. 134 Baud Rate Generator........................................................................................ 134 Synchronous Mode (Mode 0) ........................................................................... 135 Asynchronous Modes (Modes 1, 2 and 3) .........................................................137 Multiprocessor Communication (Modes 2 and 3) ............................................. 140 Automatic Address Recognition........................................................................ 140 Interrupt .............................................................................................................142 Registers............................................................................................................143
Synchronous Peripheral Interface .................................................. 146
Description.........................................................................................................147 Interrupt ............................................................................................................ 151 Configuration .....................................................................................................152 Registers............................................................................................................156
Two-wire Interface (TWI) Controller ................................................ 158
Description........................................................................................................ 158 Registers........................................................................................................... 172
Analog to Digital Converter ............................................................. 174
Description........................................................................................................ 174 Registers............................................................................................................177
Keyboard Interface ........................................................................... 179
Description........................................................................................................ 179
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Registers............................................................................................................180
Electrical Characteristics ................................................................. 181
Absolute Maximum Rating................................................................................ DC Characteristics............................................................................................ AC Characteristics ............................................................................................ SPI Interface ..................................................................................................... 181 181 186 190
Ordering Information ........................................................................ 201 Package Information ........................................................................ 202
TQFP80 ............................................................................................................ 202 BGA81 .............................................................................................................. 203 PLCC84 ............................................................................................................ 204
Datasheet Change Log for AT8xC51SND1C .................................. 205
Changes from 4109D-10/02 to 4109E-06/03.................................................... 205
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